w65c816s Western Design Center, Inc., w65c816s Datasheet
w65c816s
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... Aug.3, 2009 W65C816S 8/16–bit Microprocessor ...
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... The sale of any WDC product is subject to all WDC Terms and Conditions of Sales and Sales Policies, copies of which are available upon request. Copyright (C) 1981-2009 by The Western Design Center, Inc. All rights reserved, including the right of reproduction in whole or in part in any form. ...
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... INTRODUCTION ...................................................................................................... 7 1.1 Features of the W65C816S ......................................................................................................... 7 2 W65C816S FUNCTIONAL DESCRIPTION ............................................................. 8 2.1 Instruction Register (IR) ............................................................................................................. 8 2.2 Timing Control Unit (TCU) .......................................................................................................... 8 2.3 Arithmetic and Logic Unit (ALU) ................................................................................................ 8 2.4 Accumulator (A) .......................................................................................................................... 8 2.5 Data Bank Register (DBR) .......................................................................................................... 8 2.6 Direct (D) ...................................................................................................................................... 9 2.7 Index (X and Y) ............................................................................................................................ 9 ...
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... Stack Relative Indirect Indexed-(d,s),y.................................................................................... 24 4 TIMING, AC AND DC CHARACTERISTICS ......................................................... 26 4.1 Absolute Maximum Ratings ..................................................................................................... 26 4.2 DC Characteristics TA = -40°C to +85°C ................................................................................ 26 5 OPERATION TABLES........................................................................................... 31 6 RECOMMENDED W65C816S ASSEMBLER SYNTAX STANDARDS ................. 47 6.1 Directives ................................................................................................................................... 47 6.2 Comments .................................................................................................................................. 47 6.3 The Source Line ........................................................................................................................ 47 6.3.1 The Label Field .................................................................................................................... 47 ...
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HARD CORE MODEL............................................................................................ 56 8.1 W65C816 Core Information ...................................................................................................... 56 9 SOFT CORE RTL MODEL .................................................................................... 56 9.1 W65C816 Synthesizable RTL-Code in Verilog HDL ............................................................... 56 10 ORDERING INFORMATION ............................................................................... 57 ...
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... Table 5-7 Instruction Operation…………………………………………………..………………………………38 Table 6-1 Alternate Mnemonics ................................................................................................................. 48 Table 6-2 Address Mode Formats ............................................................................................................. 49 Table 6-3 Byte Selection Operator ............................................................................................................. 50 Table 7-1 Caveats ...................................................................................................................................... 51 Figure 2-1 W65C816S Internal Architecture Simplified Block Diagram ..................................................... 10 Figure 2-2 W65C816S 44 Pin PLCC Pinout .............................................................................................. 12 Figure 2-3 W65C816S 40 Pin PDIP Pinout ............................................................................................... 12 Figure 4-1 General Timing Diagram .......................................................................................................... 30 Figure 5-1 Bank Address Latching Circuit .................................................................................................... 46 ...
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... As shown in the W65C816S Processor Programming Model, Table 2-1, the Accumulator, ALU, X and Y Index registers, and Stack Pointer register have all been extended to 16 bits. A new 16-bit Direct Page register augments the Direct Page addressing mode (formerly Zero Page addressing) ...
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... In Emulation mode, the W65C816S offers many advantages, including full software compatibility with W65C02S coding. Internal organization of the W65C816S can be divided into two parts: 1) The Register Section and 2) The Control Section. Instructions obtained from program memory are executed by implementing a series of data transfers within the Register Section ...
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... The Emulation (E) select and the Break (B) flags are accessible only through the Processor Status Register. The Emulation mode select flag is selected by the Exchange Carry and Emulation Bits (XCE) instruction. Table 8-1, W65C816S Compatibility Information, illustrates the features of the Native (E=0) and Emulation (E=1) modes. The M and X flags are always equal to one in Emulation mode. When an interrupt occurs during Emulation mode, the Break flag is written to stack memory as bit 4 of the Processor Status Register ...
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... A0-A7 A8-A15 D0-D7 BE Figure 2-1 W65C816S Internal Architecture Simplified Block Diagram INDEX X (16 BITS) INDEX Y (16 BITS) STACK POINTER (S) (16 BITS) ALU (16 BITS) TRANSFER SWITCHES ACCUMULATOR (C) (16 BITS) (A) (8 BITS) (B) (8 BITS) PROG. COUNTER (PC) (16 BITS) DIRECT (D) (16 BITS) PROG. BANK (PBR) (8 BITS) DATA BANK (DBR) ...
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... Table 2-1 W65C816S Microprocessor Programming Model 11 ...
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... Pin Function Description VPB RDY ABORT IRQB MLB NMIB VPA VDD A10 A11 Figure 2-2 W65C816S 40 Pin PDIP Pinout NMIB VPA VDD Figure 2-3 W65C816S 44 Pin PLCC Pinout RESB VDA ...
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... The sixteen Address Bus output lines along with the bank address (multiplexed on the first half cycle of the Data Bus (D0-D7) pins) form the 24-bit Address Bus for memory and I/O exchange on the Data Bus. When using the W65C816S, the address lines may be set to the high impedance state by the Bus Enable (BE) signal. ...
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Data/Bank Address Bus (D0-D7) The Data/Bank Address Bus pins provide both the Bank Address and Data. The bank address is present during the first half of a memory cycle, and the data value is read or written during the ...
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Non-Maskable Interrupt (NMIB) A negative transition on the non-maskable Interrupt input initiates an interrupt sequence. A high to low transition initiates an interrupt sequence after the current instruction is completed. The Wait for Interrupt instruction may be executed to ...
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Reset (RESB) The Reset active low input is used to initialize the microprocessor and start program execution. The Reset input buffer has hysteresis such that a simple R-C timing circuit may be used with the internal pull-up device. The ...
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... ADDRESSING MODES The W65C816S is capable of directly addressing 16 MBytes of memory. This address space has special significance within certain addressing modes, as follows: 3.1 Reset and Interrupt Vectors The Reset and Interrupt Vectors use the majority of the fixed addresses between 00FFE0 and 00FFFF. 3.2 Stack The Stack may be use memory from 000000 to 00FFFF. The effective address of Stack and Stack Relative addressing modes will be always be within this range ...
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Absolute-a With Absolute addressing the second and third bytes of the instruction form the low order 16 bits of the effective address. The Data Bank Register contains the high order 8 bits of the operand address. 3.5.2 Absolute Indexed ...
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Absolute Indirect-(a) With Absolute Indirect addressing the second and third bytes of the instruction form an address to a pointer in Bank 0. The Program Counter is loaded with the first and second bytes at this pointer. With the ...
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Block Move-xyc Block Move (xyc) addressing is used by the Block Move instructions. The second byte of the instruction contains the high-order 8 bits of the destination address and the Y Index Register contains the low- order 16 bits ...
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Direct Indexed with X-d,x With Direct Indexed with X (d,x) addressing the second byte of the instruction is added to the sum of the Direct Register and the X Index Register to form the 16-bit effective address. The operand ...
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Direct Indirect Long Indexed-[d],y With Direct Indirect Long Indexed ([d],y) addressing the 24-bit base address is pointed to by the sum of the second byte of the instruction and the Direct Register. The effective address is this 24-bit base ...
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Direct-d With Direct (d) addressing the second byte of the instruction is added to the Direct Register (D) to form the effective address. An additional cycle is required when the Direct Register is not page aligned (DL not equal ...
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Stack Relative-d,s With Stack Relative (d,s) addressing the low-order 16 bits of the effective address is formed from the sum of the second byte of the instruction and the stack pointer. The high-order 8 bits of the effective address ...
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... Memory Utilization in Number of Program Sequence Bytes Original 8-bit New NMOS W65C816S 6502 ...
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TIMING, AC AND DC CHARACTERISTICS 4.1 Absolute Maximum Ratings This device contains input protection against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of voltages higher than the maximum rating. ...
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Figure 4-1 IDD vs. VDD Figure 4-2 F Max vs. VDD 27 ...
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... Table 4-2 W65C816S AC Characteristics 5.0 +/- 5% Symbol Parameter Min 4.75 VDD 70 tCYC Cycle Time 35 tPWL Clock Pulse Width Low 35 tPWH Clock Pulse Width High tF,tR Fall Time, Rise Time 10 tAH A0-A15 Hold Time tADS A0-A15 Setup Time 10 tBH BA0-BA7 Hold Time tBAS BA0-BA7 Setup Time 30 tACC ...
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PHI2 RWB, MLB, VPB A0-A15, VDA VPA t ADS READ DATA, BA0-BA7 t DHR t BAS WRITE DATA, BA0-BA7 t DHW IRQB, NMIB, RESB, RDY ABORTB M M Timing measurement points are ...
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... OPERATION TABLES Table 5-1 W65C816S Instruction Set-Alphabetical Sequence 1. ADC Add Memory to Accumulator with Carry 2. AND "AND" Memory with Accumulator 3. ASL Shift One Bit Left, Memory or Accumulator 4. BCC Branch on Carry Clear (C=0) 5. BCS Branch on Carry Set (C=1) 6. BEQ Branch if Equal (Z=1) 7. BIT Bit Test 8. BMI Branch if Result Minus (N=1) 9 ...
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Table 5-2 Emulation Mode Vector Locations (8-bit Mode) Address 00FFFE,F 00FFFC,D 00FFFA,B 00FFF8,9 00FFF6,7 00FFF4,5 00FFF2,3 00FFF0,1 Table 5-3 Native Mode Vector Locations (16-bit Mode) Address 00FFEE,F 00FFEC,D 00FFEA,B 00FFE8,9 00FFE6,7 00FFE4,5 00FFE2,3 00FFE0,1 The VP output is low during ...
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BRK ORA COP ORA TSB 0 s (d,x) s d,s d 7,2 6,2 7,2 4,2 5,2 BPL ORA ORA ORA TRB 1 r (d),y (d) (d,s),y d 2,2 5,2 5,2 7,2 5,2 ...
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Table 5-5 Operation, Operation Codes, and Status Register Operation Addressing Mode A+M+C→ ADC A^M→ AND C←15/7 6 … 10 ← ASL Branch BCC ...
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Operation Addressing Mode → LDX M → LDY 0 → 15/7 6 … → LSR M→M NEGATIVE MVN* M→M POSITIVE MVP* No Operation ...
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Operation Addressing Mode → STY 00 → STZ A → X TAX A → Y TAY C → D TCD* C → S TCS* D → C TDC* 1C TRB ...
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Table 5-6 Addressing Mode Symbol Table Symbol Addressing Mode # immediate A accumulator r program counter relative rl program counter relative long I implied s stack d direct d,x direct indexed with x d,y direct indexed with y (d) direct ...
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Table 5-7 Instruction Operation (continued on following 6 pages) Address Mode 1a. Absolute a ADC, AND, BIT, CMP, CPX, CPY, EOR, LDA, LDX LDY ORA, SBC, STA, STX, STY, STZ, 18 OpCodes, 3 bytes, 4 & 5 cycles 1b. Absolute ...
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Address Mode 4a. Absolute Long al ADC, AND, CMP, EOR, LDA, ORA, SBC, STA, 8 OpCodes, 4 bytes, 5 & 6 cycles 4b. Absolute Long (JUMP) al JMP 1 OpCode, 4 bytes, 4 cycles 4c. Absolute Long (JUMP to Subroutine ...
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Address Mode 9a. Block Move Negative (backward) xyc MVN 1 Op Code N-2 3 bytes Byte 7 cycles C=2 x=Source Address y=Destination c=# of bytes to move-1 x,y Increment FFFFF Source End Dest. End Source Start N Byte 000000 C=0 ...
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Address Mode 10a. Direct d ADC AND BIT, CMP, CPX, CPY ,EOR, LDA, LDX, LDY, ORA, SBC, STA, STX, STY, STZ 16 OpCodes, 2 bytes & 5 cycles 10b. Direct (R-M-W)d ASL, DEC, INC, LSR, ROL, ROR, TRB, ...
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Address Mode Note 16a. Direct, X d,x ADC, AND, BIT, CMP, EOR, LDA LDY, ORA, SBC, STA, STY, STZ, (2) 12 OpCodes,2 bytes, 4,5,and 6 cycles (1) 16b. Direct, X (R-M-W) d,x ASL, DEC, INC, LSR, ROL, ROR, 6 OpCodes, ...
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Address Mode 20. Relative r BCC, BCS, BEQ, BMI, BNE, BPL, BRA, BVC,BVS 9 OpCodes, 2 bytes, 2,3 and 4 cycles 21. Relative Long rl BRL 1 OpCode, 3 bytes, 4 cycles 22a. Stack s ABORT, IRQ, NMI, RES 4 ...
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Address Mode 22g. Stack s RTI 1 Op Code, 1 byte, 6 and 7 cycles (different order fromN6502) 22h. Stack s RTS 1 OpCode, 1 byte, 6 cycles 22i. Stack s RTL 1 Op Code, 1 byte, 6 cycles 22j. ...
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... Notes: Be aware that notes #4-7, 9 and 10 apply to the W65C02S and W65C816S. All other notes apply to the W65C816S only. 1. Add 1 byte (for immediate only) for M=0 or X=0 (i.e. 16-bit data), add 1 cycle for M=0 or X=0. REP, SEP are always 3 cycle instructions and VPA is low during the third cycle. The address bus is PC+1 during the third cycle ...
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Figure 5-1 Bank Address Latching Circuit 46 ...
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... Other special characters may be used as well. 6.3 The Source Line Any line which causes the generation of a single W65C816S machine language instruction should be divided into four fields: a label field, the operation code, the operand, the comment field. 6.3.1 The Label Field The label field begins in column one of the line ...
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Table 6-1 Alternate Mnemonics 6.3.2.4 JSL should be recognized as equivalent to JSR when it is specified with a long absolute address forced. JML is equivalent to JMP with long addressing forced. 6.3.3 The Operand Field The operand field may ...
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Addressing Mode Format Immediate #d #a #al #EXT #<d #<a #<al #<EXT #>d #>a #>al #>EXT #^d #^a #^al #^EXT Absolute ! !al !EXT EXT Absolute Long >d >a >al al >EXT Direct Page d <d <a <al ...
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Note that the operand does not determine whether or not immediate address loads one or two bytes, this is determined by the setting of the status register. This forces the requirement for a directive or directives that tell the ...
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... Modify and Write cycles cycles of Extra read of last Extra read of last instruction fetch instruction fetch Processor stops Processor stops W65C816S Always page 1 8 bits when(E=1), 16 bits when E=0 Indexed page zero always in page 0 (E=1), Cross page (E=0) Indexed page zero always in page 0 (E=1), Cross page ...
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... The Absolute Indexed addressing modes are used to address data outside the direct addressing range. The W65C02S addressing range is 0000 to FFFF. Indexing from page FFXX may result in a 00YY data fetch when using the W65C02S. In contrast, indexing from page ZZFFXX may result in ZZ+1,00YY when using the W65C816S. 7.4 ABORTB Input 7 ...
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... When in the Emulation mode, the MVP and MVN instructions use the X and Y Index Registers for the memory address. Also, the MVP and MVN instructions can only move data within the memory range 0000 (Source Bank) to 00FF (Destination Bank) for the W65C816S, and 0000 to 00FF for the emulation mode. ...
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... RDY Pulled During Write The NMOS 6502 does not stop during a write operation. W65C816S do stop during write operations 7.18 MVN and MVP Affects on the Data Bank Register The MVN and MVP instructions change the Data Bank Register to the value of the second byte of the instruction (destination bank address) ...
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Interrupt Priorities The following interrupt priorities will be in effect should more than one interrupt occur at the same time: Priority Highest Priority 1. RESB Lower 2. Abortb’ Lower 3 NMIB Lowest 4 IRQB 7.20 Transfers from 8-Bit to ...
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... The RTL-Code (Register Transfer Level) in Verilog is a synthesizable model. The behavior of this model is equivalent to the original W65C816S hard core. The W65C816S RTL-Code is available as the core model and the W65C816S standard chip model. The standard chip model includes the soft core and the buffer ring in RTL-Code. Synthesizable cores are useful in ASIC design. ...
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... Ship and store product in conductive shipping tubes or conductive foam plastic. Never ship or store product in non-conductive plastic containers or non-conductive plastic foam material. 2. Handle MOS parts only at conductive work stations. 3. Ground all assembly and repair tools. W65C816S6PLG-14 licenses, contact us at: The Western Design Center, Inc. 2166 East Brown Road Mesa, Arizona 85213 USA Fax: 480-835-6442 Info@WesternDesignCenter ...