w65c816s Western Design Center, Inc., w65c816s Datasheet - Page 45

• Manufacturer Part Number: w65c816s
• Description: W65c816s 8/16?bit Microprocessor
• Manufacturer: Western Design Center, Inc.

Notes: Be aware that notes #4-7, 9 and 10 apply to the W65C02S and W65C816S. All other notes apply to the
1. Add 1 byte (for immediate only) for M=0 or X=0 (i.e. 16-bit data), add 1 cycle for M=0 or X=0. REP, SEP are
2. Add 1 cycle for direct register low (DL) not equal 0.
3. Special case for aborting instruction. This is the last cycle which may be aborted or the Status, PBR or
4. Add 1 cycle for indexing across page boundaries, or write, or X=0. When X=1 or in the emulation mode, this
5. Add 1 cycle if branch is taken.
6. Add 1 cycle if branch is taken across page boundaries in 6502 emulation mode (E=1).
7. Subtract 1 cycle for 6502 emulation mode (E=1).
8. Add 1 cycle for REP, SEP.
9. Wait at cycle 2 for 2 cycles after NMIB or IRQB active input.
10. RWB remains high during Reset.
11. BRK bit 4 equals "0" in Emulation mode.
12. PHP and PLP.
13. Some OpCodes shown are compatible only with the W65C816S.
14. VDA and VPA are not valid outputs on the W65C02S but are valid on the W65C816S. The two signals,
15. The PBR is only applicable to the W65C816S.
16. COP Latches.
17. In the emulation mode, during a R-M-W instruction the RWB is low during both write and modify cycles.
W65C816S only.
always 3 cycle instructions and VPA is low during the third cycle. The address bus is PC+1 during the third
cycle.
DBRregisters will be updated.
cycle contains invalid addresses.
VDA and VPA, are included to point out the upward compatibility to the W65C816S. When VDA and VPA
are both a one level, this is equivalent to SYNC being a one level.
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