w65c816s Western Design Center, Inc., w65c816s Datasheet - Page 16

• Manufacturer Part Number: w65c816s
• Description: W65c816s 8/16?bit Microprocessor
• Manufacturer: Western Design Center, Inc.

2.25
The Reset active low input is used to initialize the microprocessor and start program execution. The Reset
input buffer has hysteresis such that a simple R-C timing circuit may be used with the internal pull-up
device. The RESB signal must be held low for at least two clock cycles after VDD reaches operating
voltage. Ready (RDY) has no effect while RESB is being held low. The stack pointer must be initialized by
the user's software. During the Reset conditioning period the following processor initialization takes place:
When Reset is brought high, an interrupt sequence is initiated
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2.26 Valid Data Address (VDA) and Valid Program Address (VPA)
The Valid Data Address and Valid Program Address output signals indicate valid memory addresses when
high and are used for memory or I/O address qualification.
2.27 VDD and VSS
VDD is the positive supply voltage and VSS is system logic ground.
2.28 Vector Pull (VPB)
The Vector Pull active low output indicates that a vector location is being addressed during an interrupt
sequence. VPB is low during the last two interrupt sequence cycles, during which time the processor loads
the PC with the interrupt handler vector location. The VPB signal may be used to select and prioritize
interrupts from several sources by modifying the vector addresses.
VDA
0
0
1
1
Reset (RESB)
STP and WAI instructions are cleared
RWB remains in the high state during the stack address cycles.
The Reset vector address is 00FFFC,D.(see Table 6-1 for Vectors)
PC is loaded with the contents of 00FFFC,D
VPA
0
1
0
1
Internal Operation Address and Data Bus available. The Address Bus may be invalid.
Valid program address-may be used for program cache control.
Valid data address-may be used for data cache control.
Opcode fetch-may be used for program cache control and single step control.
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