w65c816s Western Design Center, Inc., w65c816s Datasheet - Page 13

• Manufacturer Part Number: w65c816s
• Description: W65c816s 8/16?bit Microprocessor
• Manufacturer: Western Design Center, Inc.

2.13 Abort (ABORTB)
The Abort negative pulse active input is used to abort instructions (usually due to an Address Bus
condition).
instruction. Upon completion of this instruction, an interrupt sequence is initiated. The location of the
aborted opcode is stored as the return address in stack memory. The Abort vector address is 00FFF8,9
(Emulation mode) or 00FFE8,9 (Native mode). Note that ABORTB is a pulse sensitive signal; i.e., an
abort will occur whenever there is a negative pulse (or level) on the ABORTB pin during a PHI2 clock.
2.14 Address Bus (A0-A15)
The sixteen Address Bus output lines along with the bank address (multiplexed on the first half cycle of the
Data Bus (D0-D7) pins) form the 24-bit Address Bus for memory and I/O exchange on the Data Bus. When
using the W65C816S, the address lines may be set to the high impedance state by the Bus Enable (BE)
signal.
2.15 Bus Enable (BE)
The Bus Enable input signal allows external control of the Address and Data Buffers, as well as the RWB
signal. With Bus Enable high, the RWB and Address Buffers are active. The Data/Address Buffers are
active during the first half of every cycle and the second half of a write cycle. When BE is low, these buffers
are disabled. Bus Enable is an asynchronous signal.
A negative transition will inhibit modification of any internal register during the current
A0-A15
ABORTB
BE
PHI2
D0-D7
E
IRQB
MLB
MX
NC
NMIB
RDY
RESB
RWB
VDA
VPB
VPA
VDD
VSS
Pin
Table 2-2 Pin Function Table
Address Bus
Abort Input
Bus Enable
Phase 2 In Clock
Data Bus/Bank Address Bus
Emulation OR Native Mode Select
Interrupt Request
Memory Lock
Memory and Index Register Mode Select
No Connect
Non-Maskable Interrupt
Ready
Reset
Read/Write
Valid Data Address
Vector Pull
Valid Program Address
Positive Power Supply
Internal Logic Ground
Description
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