w65c51n Western Design Center, Inc., w65c51n Datasheet
w65c51n
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w65c51n Summary of contents
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... March 30, 2010 Asynchronous Communications Interface Adapter (ACIA) W65C51N ...
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... The sale of any WDC product is subject to all WDC Terms and Conditions of Sales and Sales Policies, copies of which are available upon request. Copyright ©1981 2010 by The Western Design Center, Inc. All rights reserved, including the right of reproduction, in whole part, in any form. 2 ...
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... INTRODUCTION The WDC CMOS W65C51N Asynchronous Communications Interface Adapter (ACIA) provides an easily implemented, program controlled interface between 8-bit microprocessor based systems and serial communication data sets and modems. The ACIA has an internal baud rate generator. This feature eliminates the need for multiple component support circuits, a crystal being the only other part required ...
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... RS0 B U RS1 S PHI2 TIMING & CONTROL RESB Figure 2 ACIA Internal Organization RWB PHI2 IRQB 1 RxC D7 2 XTLI D6 3 XTL0 D5 W65C51N 4 RTSB D4 5 CTSB D3 6 TxD D2 7 DTRB DSRB DCDB VDD Figure 1b 32 Pin LQFP Pin Out TRANSMIT CONTROL ...
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FUNCTIONAL DESCRIPTION A block diagram of the ACIA is presented in Figure 3 followed by a description of each functional element of the device. DATA BUS BUFFERS The Data Bus Buffer interfaces the system data lines to the internal data ...
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STATUS REGISTER The Status Register indicates the state of interrupt conditions and other non-interrupt status lines. The interrupt conditions are the Data Set Ready, Data Carrier Detect, Transmitter Data Register Empty and Receiver Data Register Full as reported in bits ...
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STATUS REGISTER BIT DESCRIPTION Parity error (Bit 0) Framing Error (Bit 1) and Overrun (Bit 2) None of these bits causes a processor interrupt to occur but, they are normally checked at the time the Receiver Data Register is read ...
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CONTROL REGISTER The Control Register selects the desired baud rate, frequency source, word length and the number of stop bits WL1 WL0 RCS SBR N 3 Bit 7 Stop Bit Number (SBN) 0 ...
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CONTROL REGISTER BIT DESCRIPTION Selected Baud Rate (Bits These bits select the Transmitter baud rate, which can be at 1/16 an external clock rate or one of 15 other rates controlled by the internal baud rate ...
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COMMAND REGISTER The Command Register controls specific modes and functions PMC PME REM PMC1 PMC0 TIC1 Bits 7-6 Parity Mode Control (PMC Receiver Odd parity checked 0 1 Receiver Even parity ...
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... Receiver bit enables generation and checking of parity bits. Parity Mode Control (Bits 6, 7) These bits determine the type of parity generated by the Transmitter (W65C51N device currently will only generate a MARK parity bit) and the type of parity check done by the Receiver (even, odd or no check). ...
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INTERFACE SIGNALS Figure 4 shows the ACIA interface signals associated with the microprocessor and the modem. TRANSMIT CONTROL DATA BUS D0-D7 BUFFERS TRANSMIT DATA & INTERRUPT IRQB SHIFT LOGIC REGISTERS STATUS RWB REGISTER CS0 I/O CONTROL CS1B BAUD RATE RS0 ...
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The IRQB pin is an interrupt output from the interrupt control logic open drain output, permitting several devices to be connected to the common IRQB microprocessor input. Normally a high level, IRQB goes low when an interrupt ...
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ACIA/MODEM INTERFACE Crystal Pins (XTLI, XTLO) These pins are normally directly connected to the external crystal (1.8432 MHz) to derive the various baud rates. Alternatively, an externally generated clock can drive the XTLI pin, in which case the XTLO pin ...
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TRANSMITTER AND RECEIVER OPERATION Continuous Data Transmit In the normal operating mode, the interrupt request output (IRQB) signals when the ACIA is ready to accept the next data word to be transmitted. This interrupt occurs at the beginning of the ...
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Transmit Data Register Not Loaded by Processor If the processor is unable to load the Transmit Data Register in the allocated time, then the TxD line goes to the “MARK” condition until the data is loaded. IRQB interrupts continue to ...
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Effect of Overrun on Receiver If the processor does not read the Receiver Data Register in the allocated time, then, when the following interrupt occurs, the new data word is not transferred to the Receiver Data Register, but the Overrun ...
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Effect of CTSB on Echo Mode Operation In Echo Mode, the Receiver operation is unaffected by CTSB, however, the Transmitter is affected when CTSB goes high, ie., the TxD line immediately goes to a continuous “Mark” condition. In this case, ...
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Overrun in Echo Mode If Overrun occurs in Echo Mode, the Receiver is affected the same way as a normal overrun in Receive Mode. For the retransmitted data, when overrun occurs, the TxD line goes to the “MARK” condition until ...
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Effect of DCDB on Receiver DCDB is a modem output indicating the status of the carrier-frequency-detection circuit of the modem. This line goes high for a loss of carrier. Normally, when this occurs, the modem will stop transmitting data some ...
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Transmit Continuous “BREAK” This mode is selected via the ACIA Command Register and causes the Transmitter to send continuous “BREAK” characters, beginning with the next character transmitted. At least one full “BREAK” character will be transmitted, even if the processor ...
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STATUS REGISTER OPERATION Because of the special functions of the various status bits, there is a suggested sequence for checking them. When an interrupt occurs, the ACIA should be interrogated as follows: 1. Read Status Register This operation automatically clears ...
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Precautions to consider with the crystal oscillator circuit: a) The external crystal should be a “series” mode crystal. b) The XTLI input may be used as an external clock input. The unused pin (XTLO) must be floating and may ...
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Table 2 Divisor Selection Control Divisor Selected Register for the Internal Bits Counter Divisor Selected 36,864 24,576 16,769 0 ...
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DIAGNOSTIC LOOP-BACK OPERATING MODES A simplified block diagram for a system incorporating an ACIA is shown in Figure 18. It may be desirable to include in the system a facility for “loop-back” testing, of which there are two kinds. 1. ...
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MICRO- PROCESSOR PROGRAM ROM RTSB DTRB TxD LLB SEL 1Y 2Y STB 3Y 4Y 74157 Figure 19 Loop-Back Circuit Schematic SYSTEM I/O RAM CONTROL I/O TO DATA LINK Figure 18 Simplified ...
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... EXTERNAL 6 6 XTL1 XTL1 CLOCK 1MΩ OPEN XTL2 XTL2 CIRCUIT 7 7 30pF INTERNAL CLOCK EXTERNAL CLOCK Figure 20 Clock Generation W65C51N 27 ...
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READ TIMING DIAGRAM Timing diagrams for transmit with external clock, receive with external clock and IRQB generation are shown in Figures 21, 22 and 23 respectively. The corresponding timing characteristics are listed in Table 3. Table 2 Transmit/Receive Characteristics Characteristic ...
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CCY XTLI t CH (TRANSMIT CLOCK INPUT TxD NOTE: TxD RATE IS 1/16 TxC RATE Figure 21 Transmit Timing with External Clock t CCY RxC (INPUT NOTE: RxD RATE IS 1/16 RxC RATE Figure 22 ...
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Parameter PHI2 Cycle Time PHI2 Pulse Width Address Set-Up Time Address Hold Time RWB Set-Up Time RWB Hold Time Data Bus Set-Up time Data Bus Hold Time Read Access Time (Valid Data) Read Hold Time Bus Active Time (Invalid Data) ...
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ABSOLUTE MAXIMUM RATINGS* Parameter Symbo Value l Supply Voltage -0.3 to +7. Input Voltage V -0 Output Voltage V -0 +0.3V OUT CC Operating T A Temp +70 Commercial -40 ...
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PIN NO.1 IDENT. (1.470) (1.440) (.065) (.045) (.023) .032 REF. (.110) (.085) (.015) (.090) (.065) Figure 26 28 Pin Plastic Dip Package Dimensions Figure 27 32 Pin Low-Profile Quad Flat Pack (LQFP) Package Dimensions (.550) (.530) (.160) (.140) (.610) (.590) ...
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... W65C51N6TPG-14 Samples Errata Sheet for Date Code: The current engineering sample is provided pin PDIP package. This information below describes the current known errors and improvements with the current W65C51N ACIA Engineering Samples found by WDC. Please contact WDC with any other errors found while evaluating these samples ...
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... Ship and store product in conductive shipping tubes or conductive foam plastic. Never ship or store product in non-conductive plastic containers or non-conductive plastic foam material. 2. Handle MOS parts only at conductive workstations. 3. Ground all assembly and repair tools. W65C51N6TPG-14 2166 East Brown Road Mesa, Arizona 85213 USA Fax: 480-835-6442 W65C 51N ...