cx29600 Mindspeed Technologies, cx29600 Datasheet - Page 87
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cx29600
Manufacturer Part Number
cx29600
Description
Optiphytm - M155 Sts-3 Sonet/sdh Multiplexer
Manufacturer
Mindspeed Technologies
Datasheet
1.CX29600.pdf
(219 pages)
- Current page: 87 of 219
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CX29600
CX29600 Data Sheet
2.6.2 Signals
Table 2-24. Signal Definition for Transmit Interface
Table 2-25. Signal Definition for Receive Interface
29600-DSH-001-B
Tables 2-24
interface. There are a total of 26 signals required to implement each SI-Bus
interface.
TxHSClk
TxClk
TxData[7:0]
TxStart
TxPrty
RxHSClk
RxClk
RxData[7:0]
RxStart[3:1]
RxPrty
Signal
Signal
Mindspeed Technologies
and
The clock signal is generated by the CX29600 and supplied to the slave.
Nominal rate is 51.84 MHz.
The clock signal is generated by the CX29600 and supplied to the slave.
Nominal rate is 19.44 MHz.
The 8-bit data path for transmit data from the slave device to the CX29600
device. TxData[7] is the MSB, TxData[0] is the LSB. Data is provided in
response to the TxClk signal.
The start signal, which is generated by the CX29600, indicates the start of
frame for the STS-1 frame.
Data path parity. The TxPrty parity bit serves as the odd parity bit calculated
over TxData[7:0].
The clock signal is generated by the CX29600 and supplied to the
slave. Nominal rate is 51.84 MHz. This clock is derived from the
incoming line timing for the OC3 data stream.
The clock signal is generated by the CX29600 and supplied to the
slave. Nominal rate is 19.44 MHz. This clock is derived from the
incoming line timing for the OC3 data stream.
The 8-bit data path for receive data from the CX29600 device to the
slave device. RxData[7] is the MSB, RxData[0] is the LSB. Data is
provided synchronously with the RxClk signal.
The start signals indicate the start of frame for STS-1 numbers 3,
2, and 1, respectively.
Data path parity. The RxPrty parity bit serves as the odd parity bit
calculated over RxData[7:0].
2-25
TxPrty
where ^ is the XOR operator.
RxPrty
where ^ is the XOR operator.
summarize the signals required to implement the SI-Bus
≈
≈
( TxData[7] ^ TxData[6] ^ TxData[5] ^ TxData[4] ^
( RxData[7] ^ RxData[6] ^ RxData[5] ^ RxData[4] ^
RxData[3] ^ RxData[2] ^ RxData[1] ^ RxData[0] )
TxData[3] ^ TxData[2] ^ TxData[1] ^ TxData[0] )
Description
™
Description
2.0 Functional Description
2.6 SI-Bus Interface
2-43
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