cx29600 Mindspeed Technologies, cx29600 Datasheet - Page 76

• Manufacturer Part Number: cx29600
• Description: Optiphytm - M155 Sts-3 Sonet/sdh Multiplexer
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.4 SONET/SDH Framer and Overhead Processor
Table 2-18. S1 Byte Description
2-32
2.4.3.19 M1
2.4.3.16 S1
2.4.3.17 Z1
2.4.3.18 Z2
2.4.3.20 E2
The Synchronization Status byte, S1, indicates the signal clock quality and clock
source. S1 carries the value from the TXS1 register.
bit 2) will be generated when the incoming S1 byte differs consistently from the
current value for 8 consecutive frames.
consecutively received S1 bytes differ from the current stable S1 byte. It is
cleared when the same S1 byte is received 8 times consecutively, whether this is
the S1 byte that was received previously, or it is of a new value. The S1 Unstable
status bit is reset to an active high state.
The Z1 bytes are allocated for future growth, and are set to the values of the
TXZ1b/TXZ1c registers.
interrupt (LININT bit 1) is generated when the incoming Z1 bytes differ
consistently from the current values for 3 consecutive frames.
The Z2 bytes are allocated for future growth, and are set to the values of the
TXZ2a/TXZ2b registers.
interrupt (LININT bit 0) is generated when the incoming Z2 bytes differ
consistently from the current values for 3 consecutive frames.
The Remote Error Indication (REI) byte, M1, contains the number of incoming
B2 BIP errors. Errors are reported in RXLIN bit 3 and counted in RLCNT. The
counter length is 20 bits so that saturation does not occur during a one-second
latching interval. If TXLIN bit 0 is low, M1 will contain 00h. If ERRINS bit 2 is
high, the contents of the ERRPAT register will be transmitted in the M1 byte for
one frame.
The Line Orderwire byte, E2, is allocated as orderwire channels for voice
communication. E2 is set to 00h as the default. If TXLIN bit 5 is set high, E2 will
contain data as shifted in from the TxE2 input pin.
The S1 byte is latched into the RXS1 register. A maskable interrupt (LININT
The S1 Unstable interrupt and status bit is set when 2 or more of 8
The values of the S1 byte are described in
Acronym
The Z1 bytes are latched into the RXZ1b/RXZ1c registers. A maskable
The Z2 bytes are latched into the RXZ2a/RXZ2b registers. A maskable
REI-L counts are disabled during LOS, LOF, AIS-L, or RDI-L conditions.
SMC
PRS
DUS
STU
ST2
ST3
ST4
RES
Mindspeed Technologies
Stratum 1 Traceable
Sync - Traceability Unknown
Stratum 2 Traceable
Stratum 3 Traceable
SONET Min Clock Traceable
Stratum 4 Traceable
Do not use for Sync
Reserved for Network Sync Use
Description
™
Table
Quality
Level
2-18.
—
1
2
3
4
5
5
7
CX29600 Data Sheet
29600-DSH-001-B
Lower Nibble
Bits 5,6,7,8
0001
0000
0111
1010
1100
1100
1111
1110
CX29600