cx29600 Mindspeed Technologies, cx29600 Datasheet - Page 124

• Manufacturer Part Number: cx29600
• Description: Optiphytm - M155 Sts-3 Sonet/sdh Multiplexer
• Manufacturer: Mindspeed Technologies

4.0 Registers
4.1 Memory Map
CLKREC (Clock Recovery/Loopback Control Register)
The CLKREC register controls the clock recovery and loopback testing capabilities of the device.
4-18
4-3
Bit
7
6
5
2
1
0
Default
00
0
0
0
0
0
0
hex address: 0x014
TxClkSel[1:0]
NELnLoop
ExtClkRec
TxDataSel
InvRxClk
InvTxClk
Mindspeed Technologies
SrcLoop
Name
When written to 1, the Transmit Clock output is inverted.
When written to 1, the receiver uses the falling edge of the Receive
Clock input to sample data.
When written to 0, internal clock recovery is enabled. When written
to 1, the internal clock recovery circuit is bypassed.
Transmit clock source selection.
00—synthesized from external 19.44 MHz reference
01—provided externally on LTXCLKINp/n input pins
10—sourced from recovered receive clock (loop timing)
11—sourced from recovered receive clock (loop timing)
When written to 1, the recovered serial data from the CDR is
looped back to the transmit LTxDatap/n outputs.
When written to 1, Source Loopback is enabled. This loopback
connects the line-side transmitter clock/data outputs to the
line-side receiver clock/data inputs.
When written to 1, Near End Line Loopback is enabled. This
loopback connects the line-side receive PECL clock/data inputs to
the line-side transmit PECL clock/data outputs.
TxFrameIn = pin
TxFrameIn = RxFrameOut. This is useful for DCC and E1/E2
byte loopback mode where the received section and line DCC
and E1/E2 overhead bytes are inserted into the transmit
frame.
™
Description
CX29600 Data Sheet
29600-DSH-001-B
CX29600