cx29600 Mindspeed Technologies, cx29600 Datasheet - Page 46

• Manufacturer Part Number: cx29600
• Description: Optiphytm - M155 Sts-3 Sonet/sdh Multiplexer
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.1 Line Interface
Table 2-1. PECL Input Logic Table
Table 2-2. PECL output Logic Table
2-2
2.1 Line Interface
The CX29600 communicates with the external SONET/SDH network through its
line interface, which can connect to a optical trasnceiver enabling transmission
over a fiber optic cable. The CX29600 recovers a receive clock from the
incoming receive data via an onboard PLL circuit. The receive PLL requires a
19.44 MHz reference clock to be supplied on the RxPLLClk input. A transmit
PLL synthesizes a transmit clock from a 19.44 MHz reference clock supplied on
the LTxSynRef input. The RxPLLClk and LTxSynRef may be connected to a
common 19.44 MHz clock source. The line interface is a Low Voltage
Pseudo-Emitter Coupled Logic (PECL) interface.
Emitter Coupled Logic (ECL) device. The PECL device is referenced to a
positive source, which is generally 3.3 V or 5.0 V. Use caution when interfacing
components that use different V
LTxClkO+/–, LRxClk+/–, LTxDat+/–, and LRxDat+/–, which are described in
Table
voltage difference between the two pins determines the logic value under normal
operating conditions. The input logic for this PECL interface is shown in
Table
fiber optic transceivers to the CX29600’s PECL interface.
A PECL device requires the same voltage differential on the inputs as an
The CX29600 has five pairs of differential PECL pins: LTxClkI+/–,
The output logic table for this PECL interface is shown in
See
1-4. All inputs and outputs include a positive pin and a negative pin. The
2-1.
Input +
Section 5.3.4
Mindspeed Technologies
0
0
1
1
Internal Logic Level
0
1
and
Section 5.3.5
Input –
0
1
0
1
cc
levels.
for examples on how to properly interface
™
Output +
0
1
Internal Logic Level
Invalid
Invalid
CX29600 Data Sheet
0
1
Table
29600-DSH-001-B
Output –
2-2.
1
0
CX29600