emc646sp16ak Emlsi Inc., emc646sp16ak Datasheet - Page 58

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emc646sp16ak

Manufacturer Part Number
emc646sp16ak
Description
4mx16 Bit Cellularram
Manufacturer
Emlsi Inc.
Datasheet
Figure 47. Asynchronous WRITE Followed by Burst READ
Note:
1. Non-default BCR settings for asynchronous WRITE followed by burst READ: Fixed or variable latency; latency code two (three clocks); WAIT
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning to
active LOW; WAIT asserted during delay.
fixed-latency burst READs. A refresh opportunity must be provided every t
conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
LB#/UB#
DQ[15:0]
IN/OUT
A[21:0]
ADV#
WAIT
WE#
CLK
OE#
CE#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
OH
OL
IH
IL
High-Z
Valid Address
t
AS
t
t
AVS
t
t
VP
CVS
CW
t
WC
t
WP
t
Data
AVH
t
DH
t
WPH
t
WC
Valid Address
t
t
t
AW
BW
AS
t
VS
t
t
DW
Data
WC
t
WR
CEM
Note 2
58
. A refresh opportunity is satisfied by either of the following two
t
CBPH
Valid Address
t
t
t
CSP
V
V
SP
SP
t
CEW
t
OH
OL
t
SP
SP
t
t
High-Z
t
HD
t
HD
HD
CLK
t
t
BOE
ACLK
EMC646SP16AK
Output
Don’t Care
Valid
t
KOH
4Mx16 CellularRAM
Output
Valid
Output
Valid
Output
Valid
Undefined
t
HD
High-Z
t
OHZ

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