emc646sp16ak Emlsi Inc., emc646sp16ak Datasheet - Page 54

• Manufacturer Part Number: emc646sp16ak
• Description: 4mx16 Bit Cellularram
• Manufacturer: Emlsi Inc.

Figure 43. Burst WRITE Followed by Burst READ
Note:
1. Non-default BCR settings for burst WRITE followed by burst READ: Fixed or variable latency; latency code two (three clocks); WAIT active LOW;
2. A refresh opportunity must be provided every t
WAIT asserted during delay.
HIGH, or b) CE# HIGH for longer than 15ns. CE# can stay LOW between burst READ and burst WRITE operations, but CE# must not remain
LOW longer than t
LB#/UB#
DQ[15:0]
IN/OUT
A[21:0]
ADV#
WAIT
WE#
CLK
OE#
CE#
CEM
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
. See burst interrupt diagrams for cases where CE# stays LOW between bursts.
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
OH
OL
IH
IL
High-Z
High-Z
t
t
Address
t
t
SP
SP
CSP
SP
Valid
t
t
t
HD
HD
HD
t
CLK
CEM
. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE#
t
SP
t
SP
D0
t
HD
t
HD
D1
D2
54
D3
t
HD
t
Note 2
CBPH
t
t
Address
V
V
t
SP
SP
t
SP
OH
OL
Valid
CSP
t
t
t
HD
HD
HD
High-Z
t
t
BOE
ACLK
Output
Valid
Don’t Care
EMC646SP16AK
t
KOH
Output
Valid
4Mx16 CellularRAM
Output
Valid
Output
Valid
Undefined
t
OHZ
High-Z