emc646sp16ak Emlsi Inc., emc646sp16ak Datasheet - Page 32

• Manufacturer Part Number: emc646sp16ak
• Description: 4mx16 Bit Cellularram
• Manufacturer: Emlsi Inc.

Table 15: Burst READ Cycle Timing Requirements
All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b).
Note:
1. A refresh opportunity must be provided every t
2. The High-Z timings measure a 100mV transition from either V
3. The Low-Z timings measure a 100mV transition away from the High-Z (VccQ/2) level toward either V
Address access time (fixed latency)
ADV# access time (fixed latency)
Burst to READ access time (variable latency)
CLK to output delay
Address hold from ADV# HIGH(fixed latency)
Burst OE# LOW to output delay
CE# HIGH between subsequent burst or mixed
mode operations
Maximum CE# pulse width
CE# or ADV# LOW to WAIT valid
CLK period
Chip select access time (fixed latency)
CE# setup time to active CLK edge
Hold time from active CLK edge
Chip disable to DQ and WAIT High-Z output
CLK rise or fall time
CLK to WAIT valid
Output HOLD from CLK
CLK HIGH or LOW time
Output disable to DQ High-Z output
Output enable to Low-Z output
Setup time to active CLK edge
Parameter
HIGH, or b) CE# HIGH for longer than 15ns.
CEM
. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE#
OH
Symbol
or V
t
t
t
t
t
t
t
t
AADV
t
CBPH
t
t
t
t
KHKL
KHTL
t
ACLK
CEW
t
BOE
CEM
t
t
KOH
OHZ
ABA
AVH
CSP
t
t
OLZ
t
t
CLK
CO
HD
HZ
KP
SP
AA
OL
toward VccQ/2.
Min
7.5
2.5
1.5
2
5
1
2
3
3
2
-
-
-
-
-
-
-
-
-
-
-
32
133MHz
Max
35.5
5.5
7.5
1.2
5.5
70
70
20
70
4
7
7
-
-
-
-
-
-
-
-
-
OH
9.62
or V
Min
2
5
1
3
2
2
3
3
3
-
-
-
-
-
-
-
-
-
-
-
104MHz
OL
.
Max
35.9
7.5
1.6
70
70
20
70
7
4
7
7
7
-
-
-
-
-
-
-
-
-
EMC646SP16AK
12.5
4Mx16 CellularRAM
Min
2
6
1
4
2
2
4
3
3
-
-
-
-
-
-
-
-
-
-
-
80MHZ
Max
7.5
1.8
70
70
46
20
70
9
4
7
9
7
-
-
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
1
2
2
3