m52s128168a-7tig Elite Semiconductor Memory Technology Inc., m52s128168a-7tig Datasheet - Page 8

• Manufacturer Part Number: m52s128168a-7tig
• Description: 2m X 16 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Command Truth Table
1. OP Code: Operand Code. A0~A11 & BA0~BA1 : Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
3. Auto refresh functions are same as the CBR refresh of DRAM.
4. BA0~BA1 : Bank select addresses.
5. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
7. Burst stop command is valid at every burst length.
8. DM sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
Elite Semiconductor Memory Technology Inc.
Deep Power
Precharge
Precharge Power Down
Register
Register
Address
Address
Refresh
Read &
Column
Column
Write &
A new command can be issued 2 clock cycles after EMRS or MRS.
The automatical precharge without row precharge command is meant by “Auto”..
Auto/self refresh can be issued only at all banks precharge state.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.
If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
Down
Active Power Down
Bank Active & Row Addr.
No Operation Command
Mode
COMMAND
Burst Stop
Refresh
Auto Precharge Disable
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Enable
Self
Mode Register Set
DM
Extended MRS
Bank Selection
Auto Refresh
All Banks
Entry
Exit
Entry
Exit
Entry
Entry
Exit
Exit
CKEn-1 CKEn CS
Preliminary
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
X
X
H
H
X
X
X
H
X
X
H
H
X
L
L
L
L
RP
H
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
after end of burst.
RAS
H
X
H
H
H
X
H
X
V
X
X
H
X
V
X
H
L
L
L
L
L
X
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
CAS
H
X
H
H
X
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
L
WE
H
H
X
H
H
X
X
V
X
X
H
X
V
X
H
L
L
L
L
L
L
DM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
X
Revision : 1.4
Publication Date : Sep. 2008
BA0,1
V
V
V
V
X
OP CODE
OP CODE
A10/AP
M53D128168A
Row Address
H
H
H
L
L
L
X
X
X
X
X
X
X
X
Address
Address
Column
Column
A9~A0
A11,
X
8/47
Note
1,2
1,2
4,6
3
3
3
3
4
4
4
7
5
8