m52s128168a-7tig Elite Semiconductor Memory Technology Inc., m52s128168a-7tig Datasheet - Page 16

• Manufacturer Part Number: m52s128168a-7tig
• Description: 2m X 16 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Read Interrupted by a Read
interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read
command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point
the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock.
Read Interrupted by a Write & Burst Stop
by placing the DQ’s(Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the beginning the
write operation, Burt stop command must be applied at least RU(CL) clocks ［RU means round up to the nearest integer］ before
the Write command.
Elite Semiconductor Memory Technology Inc.
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is
To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus
The following functionality establishes how a Write command may interrupt a Read burst.
1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read burst and tristate the
2. It is illegal for a Write command to interrupt a Read with autoprecharge command.
C O M M A N D
C O M M A N D
DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write
command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer].
D Q ' s
C L K
C L K
D Q S
D Q S
D Q ' s
C L K
C L K
<Burst Length = 4,
<Burst Length = 4, CAS Latency = 3>
R E A D A
R E A D
H i - Z
t
H i - Z
0
C C D ( m i n )
0
R E A D B
B u r s t S t o p
1
CAS
1
N O P
Latency = 3>
N O P
Preliminary
t
R P R E
t
D Q S C K
2
t
t
R P R E
D Q S C K
2
t
A C
D o u t A
N O P
D ou t 0
N O P
0
3
D o u t A
3
t
D o u t 1
R P S T
1
D ou t B
N O P
N O P
0
4
D o u t B
4
1
D o u t B
N O P
W R I T E
2
5
D o u t B
t
R P S T
t
W P R E S
5
t
D Q S S
t
3
W P R E
N O P
t
Revision : 1.4
Publication Date : Sep. 2008
W P R E H
Din 0
N O P
6
6
Din 1 Din 2 Din 3
N O P
M53D128168A
N O P
7
7
N O P
t
W P S T
N O P
8
16/47
8