m52s128168a-7tig Elite Semiconductor Memory Technology Inc., m52s128168a-7tig Datasheet - Page 20

• Manufacturer Part Number: m52s128168a-7tig
• Description: 2m X 16 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Write Interrupted by a Precharge & DM
access is allowed. A write recovery time (t
asserted, any residual data from the burst write cycle must be masked by DM.
C O M M A N D
required by a Mobile DDR SDRAM core to properly store a full “0” or “1” level before a Precharge operation. For Mobile DDR
SDRAM, a timing parameter, t
command to the same bank.
sampled by the input clock. Inside the Mobile DDR SDRAM, the data path is eventually synchronizes with the address path by
switching clock domains from the data strobe clock domain to the input clock domain.
parameter must reference only the clock domain that is used to time the internal write operation i.e., the input clock domain.
edge that strobes in the precharge command.
1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write
2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the
3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after t
4. In all cases, a Precharge operation cannot be initiated unless t
Elite Semiconductor Memory Technology Inc.
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column
Precharge timing for Write operations in Mobile DDR SDRAM requires enough time to allow “Write recovery” which is the time
The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is
This makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery
t
recovery is defined by t
time between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the
DQS input is still required to strobe in the state of DM. The minimum time for write recovery is defined by t
t
Bank Activate commands. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as
the earliest possible external Precharge command without interrupting the Write burst as described in 1 above.
satisfied. This includes Write with autoprecharge commands where t
autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command
which does not interrupt the burst.
WR
WR
D M
D Q S
D Q ' s
D Q ' s
D Q S
starts on the rising clock edge after the last possible DQS edge that strobed in the last valid and ends on the rising clock
C L K
C L K
+ t
<Burst Length = 8>
D M
RP
starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the
N O P
H i - Z
H i - Z
H i - Z
0
H i - Z
W RITE A
WR
.
t
t
W P R E S
D Q S S ( m i n )
WR
t
W P R E S
1
, is used to indicate the required of time between the last valid write operation and a Precharge
t
D Q S S ( m a x
D i n a 0 D i n a 1 D i n a 2 D i n a 3 D i n a 4 D i n a 5 D i n a 6 D i n a 7
t
W P R E H
t
W P R E H
N O P
D i n a 0 D i n a 1
WR
)
2
Preliminary
) is required from the last data to precharge command. When precharge command is
N O P
D i n a 2 D i n a 3
3
N O P
RAS
4
(min) [minimum Bank Activate to Precharge time] has been
RAS
N O P
t
W R
t
W R
(min) must still be satisfied such that a Write with
5
P r e c h a r g e A
Revision : 1.4
6
Publication Date : Sep. 2008
W RITE B
t
W P R E S
t
t
D Q S S ( m i n )
W P R E S
t
7
D Q S S ( m a x
M53D128168A
t
D i n b 0 D i n b 1
W P R E H
t
WR
W P R E H
N O P
.
)
D i n b 0
8
WR
+ t
20/47
RP
where