m52s128168a-7tig Elite Semiconductor Memory Technology Inc., m52s128168a-7tig Datasheet - Page 15

• Manufacturer Part Number: m52s128168a-7tig
• Description: 2m X 16 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Essential Functionality for Mobile DDR SDRAM
Burst Read Operation
read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK)
after t
burst (Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ
command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by Mobile DDR
SDRAM until the burst length is completed.
Burst Write Operation
clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst
write cycle. The first data of a burst write cycle must be applied on the DQ pins t
enabled after t
supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been
finished, any additional data supplied to the DQ pins will be ignored.
Elite Semiconductor Memory Technology Inc.
C A S L a t e n c y = 3
Burst Read operation in Mobile DDR SDRAM is in the same manner as the current Mobile DDR SDRAM such that the Burst
The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the
<Burst Length = 4>
C O M M A N D
RCD
from the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of
D Q S
D Q ' s
D Q S
D Q ' s
C L K
C L K
DQSS
C O M M A N D
<Burst Length = 4, CAS Latency = 3>
from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be
N O P
D Q ' s
C L K
D Q S
C L K
0
R E A D A
W R I T E A
0
t
D Q S S (
1
t
t
W P R E S
W P R E S
t
N O P
m i n )
t
D Q S S (
D i n 0
t
t
D S
W P R E H
W P R E H
t
N O P
Preliminary
D H
1
m a x )
D i n 0
D i n 1
2
N O P
D i n 1
D i n 2
W R I T E B
t R P R E
t D Q S C K
2
t A C
D i n 2
D i n 3
3
N O P
D o u t 0 D o u t 1 D o u t 2 D o u t 3
D i n 3
D i n 0
3
N O P
D i n 0
D i n 1
4
N O P
D i n 1
D i n 2
4
N O P
t R P S T
DS
D i n 2
D i n 3
(Data-in setup time) prior to data strobe edge
5
N O P
D i n 3
5
Revision : 1.4
N O P
Publication Date : Sep. 2008
6
N O P
6
t
t
W R
W R
M53D128168A
N O P
N O P
7
7
N O P
N O P
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8
8