m52s128168a-7tig Elite Semiconductor Memory Technology Inc., m52s128168a-7tig Datasheet - Page 19

• Manufacturer Part Number: m52s128168a-7tig
• Description: 2m X 16 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Write Interrupted by a Read & DM
clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered,
any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (t
required to avoid the data contention Mobile DDR SDRAM inside. Data that are presented on the DQ pins before the read
command is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock
edge of that of write command.
the memory.
1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where
2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediately
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory
4. If input Write data is masked by the Read command, the DQS inputs are ignored by the Mobile DDR SDRAM.
5. It is illegal for a Read command interrupt a Write with autoprecharge command.
Elite Semiconductor Memory Technology Inc.
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one
The following functionality established how a Read command may interrupt a Write burst and which input data is not written into
the Write to Read delay is 1 clock cycle is disallowed.
precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation.
controller) in time to allow the buses to turn around before the Mobile DDR SDRAM drives them during a read operation.
C O M M A N D
D M
D Q S
D Q ' s
D Q ' s
D Q S
C L K
C L K
D M
N O P
<Burst Length = 8, CAS Latency = 3>
H i - Z
H i - Z
H i - Z
0
H i - Z
t
W P R E S
W RITE
t
W P R E S
t
5)
D Q S S ( m i n )
1
5)
t
D Q S S ( m a x
D i n a 0 D i n a 1 D i n a 2 D i n a 3 D i n a 4 D i n a 5 D i n a 6 D i n a 7
N O P
D i n a 0 D i n a 1
Preliminary
)
2
N O P
D i n a 2 D i n a 3 D i n a 4 D i n a 5 D i n a 6 D i n a 7
3
N O P
4
t
t
C D L R
C D L R
R E A D
5
N O P
Revision : 1.4
Publication Date : Sep. 2008
6
N O P
7
M53D128168A
D o u t 0
D o u t 0 D o u t 1
N O P
8
D o u t 1
19/47
WTR
) is