m52s128168a-7tig Elite Semiconductor Memory Technology Inc., m52s128168a-7tig Datasheet - Page 23

• Manufacturer Part Number: m52s128168a-7tig
• Description: 2m X 16 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Write with Auto Precharge
same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping t
Auto Refresh & Self Refresh
Auto Refresh
the clock(CLK). All banks must be precharged and idle for t
external address pins is requires once this cycle has started because of the internal address counter. When the refresh cycle has
completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or
subsequent auto refresh command must be greater than or equal to the t
and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8x15.6
μm.
Elite Semiconductor Memory Technology Inc.
C O M M A N D
C K E = H i g h
If A10 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the
An auto refresh command is issued by having CS , RAS and CAS held low with CKE and WE high at the rising edge of
A maximum of eight consecutive AUTO REFRSH commands (with tRFCmin) can be posted to any given Mobile DDR SDRAM,
C O M M A N D
C L K
C L K
<Burst Length = 4>
D Q ' s
C L K
D Q S
C L K
A C T I V E
B a n k A
P R E
0
N O P
t
R P
1
A uto Pr echar ge
W rite A
Preliminary
2
Refr esh
Auto
N O P
D
IN
0
RP
3
D
(min) before the auto refresh command is applied. No control of the
I N
1
N O P
D
I N
2
t
R F C
4
RFC
D
IN
(min).
3
N O P
5
I n t e r n a l p r e c h a r g e s t a r t
t
N O P
Revision : 1.4
W R
Publication Date : Sep. 2008
6
* B a n k c a n b e r e a c t i v a t e d a t
c o m p l e t i o n o f
N O P
M53D128168A
C M D
7
t
R P
t
R P
N O P
WR
8
23/47
(min).