m52s128168a-7tig Elite Semiconductor Memory Technology Inc., m52s128168a-7tig Datasheet - Page 22

• Manufacturer Part Number: m52s128168a-7tig
• Description: 2m X 16 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
DM masking
the data mask is activated (DM high) during write operation, Mobile DDR SDRAM does not accept the corresponding data. (DM to
data-mask latency is zero) DM must be issued at the rising or falling edge of data strobe.
Read With Auto Precharge
clock later from a read with auto-precharge command when t
be delayed until t
command can not be asserted until the precharge time (t
Note : At burst read / write with auto precharge, CAS interrupt of the same bank is illegal.
Elite Semiconductor Memory Technology Inc.
The Mobile DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When
If a read with auto-precharge command is initiated, the Mobile DDR SDRAM automatically enters the precharge operation BL/2
<Burst Length = 8>
C O M M A N D
C O M M A N D
D Q S
D Q ' s
C L K
C L K
D Q ' s
D Q S
C L K
C L K
D M
RAS
A C T I V E
B a n k A
W R I T E
(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new
<Burst Length = 4, CAS Latency = 3>
0
t
H i - Z
H i - Z
W P R E S
0
N O P
t
t
D Q S S
W P R E H
1
N O P
D i n a 0 D i n a 1 D i n a 2 D i n a 3 D i n a 4 D i n a 5 D i n a 6 D i n a 7
m a s k e d b y D M = H
1
N O P
2
Preliminary
N O P
N O P
2
3
N O P
RP
Aut o Precharge
) has been satisfied
Read A
3
RAS
4
(min) is satisfied. If not, the start point of precharge operation will
N O P
N O P
4
5
Auto-Precharge starts
N O P
N O P
6
5
Dout 0 Dout 1 Dout 2 Dout 3
N O P
N O P
Revision : 1.4
7
Publication Date : Sep. 2008
t
R P
6
H i - Z
H i - Z
N O P
N O P
8
M53D128168A
7
N O P
Bank can be reactivated at
completion of t
9
N O P
8
N O P
RP 1)
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10