m52s128168a-7tig Elite Semiconductor Memory Technology Inc., m52s128168a-7tig Datasheet - Page 18

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m52s128168a-7tig

Manufacturer Part Number
m52s128168a-7tig
Description
2m X 16 Bit X 4 Banks Synchronous Dram
Manufacturer
Elite Semiconductor Memory Technology Inc.
Datasheet
ESMT
Write Interrupted by a Write
interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining
addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
Elite Semiconductor Memory Technology Inc.
<Burst Length = 4>
C O M M A N D
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the
D Q ' s
D Q S
C L K
C L K
N O P
0
WR IT E A
1
1 t
t
C C D
C K
WR IT E B
D in A
Preliminary
0
2
D in A
1
N O P
Di n B
0
3
D in B
1
N O P
Di n B
2
4
D in B
3
N O P
5
Revision : 1.4
Publication Date : Sep. 2008
N O P
6
M53D128168A
N O P
7
N O P
18/47
8

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