ace1202 Fairchild Semiconductor, ace1202 Datasheet - Page 26

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ace1202

Manufacturer Part Number
ace1202
Description
Arithmetic Controller Engine Acex ?for Low Power Applications
Manufacturer
Fairchild Semiconductor
Datasheet

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ACE1202 Product Family Rev. B.1
After the HBC has started, software must then poll the OCFLAG
for a high pulse and restore the DAT0 register and the START
signal to continue with the next data transmission.
LOOP_HI:
NXT_FRAME:
IFBIT OCFLAG, HBCNTRL
JP
JP
LD
SBIT START, HBCNTRL
OCFLAG
Bit 7
Bit 7
0
NXT_FRAME
LOOP_HI
DAT0, #092H
IOSEL
Bit 6
Bit 6
0
Clock Divider
Fixed
by 4
; Wait for OCFLAG = 1
; DAT0 = 0x92
; START / STOP = 1
START/STOP
Bit 5
Bit 5
8
TXBUSY
BPL[2:0]
Bit 4
Bit 4
StopShift
StopShift
RFCLK
RFCLK
3
3
A
Y
3
B
If software is to proceed with another data transmission, the
OCFLAG must be zero before polling for the next OCFLAG high
pulse. However, since the specification in the example requires no
other data transmission software can proceed as desired.
LOOP_LO:
IFBIT OCFLAG, HBCNTRL
JP
Etc.
Bit 3
Bit 3
3
0
NoShift
LOOP_LO
ShiftCLK
OCFLAG
b7
b7
b7
Bit 2
Bit 2
A
B
Y
FRAME[2:0]
; Wait for OCFLAG = 0
; Program proceeds as desired
BPH[2:0]
Bit 1
Bit 1
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Bit 0
Bit 0

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