ace1202 Fairchild Semiconductor, ace1202 Datasheet - Page 20

• Manufacturer Part Number: ace1202
• Description: Arithmetic Controller Engine Acex ?for Low Power Applications
• Manufacturer: Fairchild Semiconductor

ACE1202 Product Family Rev. B.1
In the PWM mode, the timer counts down at the instruction clock
rate. When an underflow occurs, the timer register is reloaded from
T1RA and the count down proceeds from the loaded value. At every
underflow, a pending flag (T1PND) located in the T1CNTRL regis-
ter is set. Software must then clear the T1PND flag and load the
T1RA register with an alternate PWM value. In addition, the timer
can be configured to toggle the T1 output bit upon underflow.
Configuring the timer to toggle T1 results in the generation of a
signal outputted from port G2 with the width and duty cycle
controlled by the values stored in the T1RA. A block diagram of the
timer’s PWM mode of operation is shown in Figure 15.
The timer has one interrupt (TMRI1) that is maskable through the
T1EN bit of the T1CNTRL register. However, the core is only
interrupted if the T1EN bit and the G (Global Interrupt enable) bit of
the SR is set. If interrupts are enabled, the timer will generate an
interrupt each time T1PND flags is set (whenever the timer
underflows provided that the pending flag was cleared.) The
interrupt service routine is responsible for proper handling of the
T1PND flag and the T1EN bit.
The interrupt will be synchronous with every rising and falling edge
of the T1 output signal. Generating interrupts only on rising or falling
edges of T1 is achievable through appropriate handling of the T1EN
bit or T1PND flag through software.
The following steps show how to properly configure Timer 1 to
operate in the PWM mode. For this example, the T1 output signal
is toggled with every timer underflow and the “high” and “low” times
for the T1 output can be set to different values. The T1 output signal
can start out either high or low depending on the configuration of
G2; the instructions below are for starting with the T1 output high.
Follow the instructions in parentheses to start the T1 output low.
Underflow
Interrupt
T1
Latch
Data
Instruction
Clock
16-bit Timer (TMR1)
16-bit Auto-Reload
Register (T1RA)
1. Configure T1 as an output by setting bit 2 of PORTGC.
2. Initialize T1 to 1 (or 0) by setting (or clearing) bit 2 of
3. Load the initial PWM high (low) time into the timer register.
4. Load the PWM low (high) time into the T1RA register.
5. Write the appropriate control value to the T1CNTRL
6. After every underflow, load T1RA with alternate values. If
- SBIT 2, PORTGC
PORTGD.
- SBIT 2, PORTGD
- LD TMR1LO, #6FH
- LD TMR1HI, #05H
- LD T1RALO, #2FH
- LD T1RAHI, #01H
register to select PWM mode with T1 toggle, to clear the
enable bit and pending flag, and to start the timer. (See
Table 12 and 13)
- LD T1CNTRL, #0B0H
the user wishes to generate an interrupt on a T1 output
transition, reset the pending flags and then enable the
interrupt using T1EN. The G bit must also be set. The
interrupt service routine must reset the pending flag and
perform whatever processing is desired.
- RBIT T1PND, T1CNTRL
- LD T1RALO, #6FH
- LD T1RAHI, #05H
Data
Bus
; Configure G2 as an output
; Set G2 high
; High (Low) for 1.391ms
; Low (High) for .303ms
; Setting the T1C0 bit starts
; T1PND equals 3
; High (Low) for 1.391ms
(1MHz clock)
(1MHz clock)
the timer
(1MHz clock)
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