ace1202 Fairchild Semiconductor, ace1202 Datasheet
ace1202
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ace1202 Summary of contents
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... fully static part fabricated using CMOS technology. The ACE1202 product family has an 8-bit microcontroller core, 64 bytes of RAM, 64 bytes of data EEPROM and 2K bytes of code EEPROM. Its on-chip peripherals include a multi-function 16-bit timer, watchdog/idle timer, and programmable undervoltage de- tection circuitry ...
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... Optional LED ACE1202 Product Family Rev. B GND LOAD VCC 8 GND SFT_IN 7 G2 NC/VCC VCC LOAD GND SFT_IN NC/VCC 9 RESET Interface ...
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... Electrostatic Discharge on all pins ACE1202 ACE12022 ACE1202E ACE12022E ACE1202V ACE1202B ACE12022B ACE1202BE ACE12022BE ACE1202BV ACE12022BV ACE1202L ACE1202 Product Family Rev. B.1 -65°C to +150°C Relative Humidity (non-condensing) -0. +0.3V EEPROM write limits CC 0.3V to 13V +300°C 2000V min 2.2 to 5.5V 0°C to 70°C 2.2 to 5.5V 0°C to 70°C 2.2 to 5.5V -40° ...
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... Output High Voltage G0, G1, G2, G4, G6 Output High Voltage G0, G1, G2, G4, G6 active current is dependent on the program code Based on a continuous IDLE looping program. ACE1202 Product Family Rev. B.1 1.8V 2.2V 2.7V 3.3V 5.5V 3.3V @ -40°C to +25°C 5.5V @ -40°C to +25°C 3.3V @ +85°C 5.5V @ +85°C 3.3V @ +125°C 5.5V @+125°C 3 ...
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... DOS t DOH SV1 SV2 LOAD1 LOAD2 LOAD3 LOAD4 V SUPERVOLTAGE ACE1202 Product Family Rev. B.1 5.0V at +25°C 0.9 3.0V to 5.5V, constant temperature 3.0V to 5.5V, full temperature range 3.0V to 4.5V, constant temperature (Note 6) (Note 7) (Note 7) (Note 7) CLOCK high time CLOCK low time SHIFT_IN setup time SHIFT_IN hold time ...
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... The following characteristics are guaranteed by design but are not 100% tested. BOR Trigger Threshold V = 1.8 to 5.5V CC The following characteristics are guaranteed by design but are not 100% tested. BOR Trigger Threshold ACE1202 Product Family Rev. B.1 Level 1 @ -40°C Level 8 @ -40°C Level 1 @ 0°C Level 8 @ 0°C Level 1 @ -25°C Level 8 @ +25°C Level 1 @ +85° ...
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... ACE1202 Product Family Rev. B.1 5.6k/100pF 6.8K/100pF 5.6k/100pF 6.8K/100pF ° Avg Min Max Avg Min Max www.fairchildsemi.com ...
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... S min BATT t S min t S actual t S max S VCC ACE1202 Product Family Rev. B actual S max Supply Voltage Battery Voltage (Nominal Operating Voltage) Minimum Time for V to Rise Actual Time for V to Rise Maximum Time for V to Rise by 1V ...
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... ACE1202 Product Family Rev. B.1 ° ° www.fairchildsemi.com ...
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... ACE1202 Product Family Rev. B.1 ° www.fairchildsemi.com ...
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... ACE1202 Product Family Rev. B.1 ° www.fairchildsemi.com ...
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... ACE1202 Product Family Rev. B.1 segment of the memory map. This modification improves the overall code efficiency of the ACEx microcontroller and takes advantage of the flexibility found on Von Neumann style ma- chines. The ACEx microcontroller has five general-purpose registers. These registers are the Accumulator (A), X-Pointer (X), Program Counter (PC), Stack Pointer (SP), and Status Register (SR) ...
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... When the subroutine is finished, a return from subroutine (RET) instruction is executed. The RET instruction pulls the previously stacked return address ACE1202 Product Family Rev. B.1 from the stack and loads it into the program counter. Execution then continues at the recovered return address. ...
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... Interrupt Pending T1EN Flags Interrupt Enable Bits ACE1202 Product Family Rev. B.1 The instruction allows the X-pointer to address any location within the data memory space. The instruction contains an 8-bit address field that directly points to the data memory space as an operand. The instruction contains an 8-bit immediate field as an operand. ...
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... M ACE1202 Product Family Rev [00, [00, [00, [00, [00, ...
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... A, [X] 1 IFGT IFGT IFNE IFNE A, [00,X] 2 IFNE A, [X] 1 IFNE IFLT IFNC 1 INC A 1 INC M 2 INC X 1 INTR 1 INVC 1 ACE1202 Product Family Rev. B.1 1 C,H,Z,N JMP 2 C,H,Z,N JMP 2 C,H,Z Z,N JSR 2 Z,N JSR C,H,Z C,H,Z,N LDC 1 ...
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... Program 0xFF6 - 0xFF7 Program 0xFF8 - 0xFF9 Program 0xFFA - 0xFFB Program 0xFFC - 0xFFD Program 0xFFE - 0xFFF ACE1202 Product Family Rev. B.1 SRAM Data RAM EEPROM Data EEPROM HBC HBCNTRL register (ACE1202-2 only) HBC PSCALE register (ACE1202-2 only) HBC HPATTERN register (ACE1202-2 only) ...
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... If set, the device will not allow any writes to occur in the upper block of data EEPROM (0x60-0x7F) 10 (3) BLSEL If set, the Brown-out Reset (BOR) voltage reference level is set to its higher range for P.N. ACE1202/ACE12022 If not set, the BOR voltage reference level is set to its lower range for P.N. ACE1202L (4) BOREN ...
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... MODE 4 Difference Capture MODE 4 Difference Capture ACE1202 Product Family Rev. B.1 default, the TMR1 is reset to 0xFFFF, T1RA is reset to 0x0000, and T1CNTRL is reset to 0x00. The timer can be started or stopped through the T1CNTRL register bit T1C0. When running, the timer counts down (decre- ments) every clock cycle. Depending on the operating mode, the timer’ ...
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... G2; the instructions below are for starting with the T1 output high. Follow the instructions in parentheses to start the T1 output low. Underflow Interrupt T1 ACE1202 Product Family Rev. B.1 1. Configure output by setting bit 2 of PORTGC. - SBIT 2, PORTGC 2. Initialize ( setting (or clearing) bit 2 of PORTGD. ...
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... Underflow Interrupt T1 ACE1202 Product Family Rev. B.1 1. Configure input by clearing bit 2 of PORTGC. - RBIT 2, PORTGC 2. Initialize T1 to input with pull-up by setting bit 2 of PORTGD. - SBIT 2, PORTGD 3. Enable the global interrupt enable bit. ...
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... Interrupt T1 Underflow Interrupt ACE1202 Product Family Rev. B.1 For example, the T1 pin can be programmed to be sensitive to a positive-going edge. When the positive edge is sensed, the TMR1 register contents is transferred to the T1RA register and a Timer 1 interrupt is generated. The Timer 1 interrupt service routine records the contents of the T1RA register, changes the edge sensitivity from positive to negative-going edge, and clears the T1PND flag ...
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... Interrupt T1 Underflow Interrupt ACE1202 Product Family Rev. B.1 Once configured, the Difference Capture timer waits for the first selected edge. when the edge transition has occurred, the 16-bit timer starts counting up based every instruction clock cycle. It will continue to count until the second selected edge transition occurs at which time the timer stops and stores the elapse time into the T1RA register ...
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... Bit 7 Bit ACE1202 Product Family Rev. B.1 reset by software or system reset. The WKINTEN bit is used in the Multi-input Wakeup/Interrupt block. See Section 8 for details. The Watchdog timer is used to reset the device and safely recover in the rare event of a processor “runaway condition.” The 12-bit Timer 0 is used as a pre-scaler for Watchdog timer ...
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... The ACE1202-2 contains a dedicated hardware bit-encoding peripheral block, Hardware Bit-Coder (HBC), for IR/RF data transmission (see Figure 21.) The HBC is completely software programmable and can be configured to emulate various bit- encoding formats. The software developer has the freedom to encode each bit of data into a desired pattern and output the encoded data at the desired frequency through either the output (TX) ports ...
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... Bit 6 OCFLAG IOSEL START/STOP ACE1202 Product Family Rev. B.1 If software is to proceed with another data transmission, the OCFLAG must be zero before polling for the next OCFLAG high pulse. However, since the specification in the example requires no other data transmission software can proceed as desired. ...
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... Period "0" "0" "1" DAT0 G2/G5 Output IR/RF CLOCK ACE1202 Product Family Rev. B.1 "0" "1" "0" "1" ¡ Software must set the START bit while OCFLAG is set in order to send another message without introducing a delay. "0" ...
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... G7 WKEDG[0:7] WKPND[0:7] 12 WKINTEN: Bit 7 of T0CNTRL ACE1202 Product Family Rev. B.1 6. Set the WKEN bits associated with the pins to be used, thus enabling those pins for the Wakeup/Interrupt function WKEN, #10H Once the Multi-Input Wakeup/Interrupt function has been config- ured, a transition sensed on any of the I/O pins will set the corresponding bit in the WKPND register ...
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... G3 is always an input with weak pull- ACE1202 Product Family Rev. B.1 (PORTGC), a port data register (PORTGD), and a port input register (PORTGP). PORTGC is used to configure the pins as inputs or outputs. A pin may be configured as an input by writing output by writing its corresponding PORTGC bit. ...
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... For further information see Application Note AN-8005. 16 During in-circuit programming, G5 must be either not connected or driven high. ACE1202 Product Family Rev. B.1 0V phase (if the timing specifications in Figure 30 are obeyed). The device will set the R bit of the Status register when the write operation has completed. The external programmer must wait for the SHIFT_OUT pin to go high before bringing the LOAD signal initiate a normal command cycle ...
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... SV1 SV2 LOAD (G3) enter prog. mode CLOCK (G1) SHIFT_IN (G4) bit 31 SHIFT_OUT (G2) (in write mode) SHIFT_OUT (G2) (in read mode) A: start of programming cycle CLOCK (G1) SHIFT_IN (G4) SHIFT_OUT (G2) ACE1202 Product Family Rev. B load1 load2 32 clock pulses bit 30 bit DIS DIH Valid t ...
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... RESET logic resetting the BOREN bit as long as the global write protect (WDIS) feature is not enabled. 18 BOR is not available on the P.N. ACE1202B/ACE12022B device The Low Battery Detect (LBD) circuit allows software to monitor the V level at the lower voltage ranges. LBD has an eight level LBD ...
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... POR output ACE1202 Product Family Rev. B.1 The external reset provides a way to properly reset the ACEx microcontroller if POR cannot be used in the application. The external reset pin contains an internal pull-up resistor. Therefore, to reset the device the reset pin should be held low for at least 2ms so that the internal clock has enough time to stabilize ...
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... Bit 7 Bit 6 undefined undefined undefined Normal Mode LD HALT, #01h Multi-Input Halt Wakeup LD PMC, #00h Resume Normal Mode ACE1202 Product Family Rev. B.1 b) CKI CKO CKI (G1) (G0) (G1 33pF In addition to the HALT mode power saving feature, the device also supports an IDLE mode operation. The device is placed into IDLE mode by setting the IDLE enable bit (EIDLE) of the HALT register through software using only the “ ...
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... X X ACE1202BVN14 X X ACE1202LM8 X X ACE1202LM8X X X ACE1202LM X X ACE1202LMX X X ACE1202LN X X ACE1202LN14 X X ACE1202 Product Family Rev. B.1 Program Operating Voltage Temperature Range Memory Size Range 1K 2K 1.8 – 2.2 – 2.7 – -40 to -40 to 5.5V 5.5V 5.5V 70°C +85C +125° ...
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... X X ACE12022BEN14 X X ACE12022BVM8 X X ACE12022BVM8X X X ACE12022BVM X X ACE12022BVMX X X ACE12022BVN X X ACE12022BVN14 X X ACE1202 Product Family Rev. B.1 Program Operating Voltage Temperature Range Memory Size Range 1K 2K 1.8 – 2.2 – 2.7 – -40 to -40 to 5.5V 5.5V 5.5V 70°C +85C +125° ...
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... ACE1202 Product Family Rev. B.1 0.228 - 0.244 (5.791 - 6.198) Lead #1 IDENT 0.053 - 0.069 (1.346 - 1.753) 8¡ Max, Typ. All leads 0.014 0.016 - 0.050 (0.356) (0.406 - 1.270) ...
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... All lead tips (0.203 - 0.254) Typ. all leads ACE1202 Product Family Rev. B 0.228 - 0.244 (5.791 - 6.198) 1 Lead #1 IDENT 0.053 - 0.069 (1.346 - 1.753) 8° Max, Typ. All leads ...
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... Italiano Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. ACE1202 Product Family Rev. B.1 circuit emulator kit that includes: Emulator board ...