ace1202 Fairchild Semiconductor, ace1202 Datasheet - Page 18

• Manufacturer Part Number: ace1202
• Description: Arithmetic Controller Engine Acex ?for Low Power Applications
• Manufacturer: Fairchild Semiconductor

ACE1202 Product Family Rev. B.1
The ACEx microcontroller device has 64 bytes of SRAM and 64
bytes of EEPROM available for data storage. The device also has
2K bytes of EEPROM for program storage. Software can read and
write to SRAM and data EEPROM but can only read from the code
EEPROM. While in normal mode, the code EEPROM is protected
from any writes. The code EEPROM can only be rewritten when
the device is in program mode and if the write disable (WDIS) bit
of the initialization register is not set to 1.
While in normal mode, the user can write to the data EEPROM
array by 1) polling the ready (R) flag of the SR, then 2) executing
the appropriate instruction. If the R flag is 1, the data EEPROM
block is ready to perform the next write. If the R flag is 0, the data
EEPROM is busy. The data EEPROM array will reset the R flag
after the completion of a write cycle. Attempts to read, write, or
(0) RDIS
(1) WDIS
(2) UBD
(3) BLSEL
(4) BOREN
(5) WDEN
(6) CMODE[1]
(7) CMODE[0]
8
9
10
If both the WDIS and RDIS bits are set, the device will no longer be able to be placed into program mode.
If the RDIS or UBD bits are not set while the WDIS bit is not set, then the RDIS and UBD bits can be reset.
The BLSEL bit is set to its appropriate level in the factory. If writing to the initialization register is necessary, be sure to maintain BLSEL set value.
Bit 7
CMODE[0]
8,9
8,9
8,9
10
Bit 6
CMODE[1]
If set, disables attempts to read the contents from the memory while in programming mode
If set, disables attempts to write new contents to the memory while in programming mode
If set, the device will not allow any writes to occur in the upper block of data EEPROM (0x60-0x7F)
If set, the Brown-out Reset (BOR) voltage reference level is set to its higher range for P.N. ACE1202/ACE12022
If not set, the BOR voltage reference level is set to its lower range for P.N. ACE1202L
If set, allows a BOR to occur if VCC falls below the voltage reference level
If set, enables the on-chip processor watchdog circuit
Clock mode select bit 1 (See Table 17)
Clock mode select bit 0 (See Table 17)
Bit 5
WDEN
Bit 4
BOREN
enter HALT/IDLE mode while the data EEPROM is busy (R = 0)
can affect the current data being written.
The ACEx microcontroller has two 8-bit wide initialization regis-
ters. These registers are read from the memory space on power-
up to initialize certain on-chip peripherals. Figure 14 provides a
detailed description of Initialization Register 1. The Initialization
Register 2 is used to trim the internal oscillator to its appropriate
frequency. This register is pre-programmed in the factory to yield
an internal instruction clock of 1MHz.
Both Initialization Registers 1 and 2 can be read from and written
to during programming mode. However, re-trimming the internal
oscillator (writing to the Initialization Register 2) once it has left the
factory is discouraged .
Bit 3
BLSEL
10
Bit 2
UBD
8,9
Bit 1
WDIS
8,9
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Bit 0
RDIS
8,9