ace1202 Fairchild Semiconductor, ace1202 Datasheet - Page 14

• Manufacturer Part Number: ace1202
• Description: Arithmetic Controller Engine Acex ?for Low Power Applications
• Manufacturer: Fairchild Semiconductor

ACE1202 Product Family Rev. B.1
The ACEx microcontroller is capable of supporting four interrupts.
Three are maskable through the G bit of the SR and the fourth
(software interrupt) is not inhibited by the G bit (see Figure 13). The
software interrupt instruction is generated by the execution of the
INTR instruction. once the INTR instruction is executed, the ACEx
core will interrupt whether the G bit is set or not. The INTR interrupt
is executed in the same manner as the other maskable interrupts
where the program counter register is stacked and the G bit is
cleared. This means, if the G bit was enabled prior to the software
interrupt the RETI instruction must be used to return from interrupt
in order to restore the G bit to its previous state. However, if the G
bit was not enabled prior to the software interrupt the RET
instruction must be used.
In case of multiple interrupts occurring at the same time, the ACEx
microcontroller core has prioritized the interrupts. The interrupt
priority sequence in shown in Table 8.
The ACEx microcontroller has seven addressing modes indexed,
indirect, direct, immediate, absolute jump, and relative jump.
The instruction allows an 8-bit unsigned offset value to be added to
the 11-LSBs of the X-pointer yielding a new effective address. This
mode can be used to address either data or program memory space.
INTR
MIW
T1
T0
Interrupt
Pending
Flags
WKPND
T1PND
T0PND
Interrupt Enable Bits
T1EN
T0INT
EN
WKINT
EN
The instruction allows the X-pointer to address any location within
the data memory space.
The instruction contains an 8-bit address field that directly points
to the data memory space as an operand.
The instruction contains an 8-bit immediate field as an operand.
This instruction has no operands associated with it.
The instruction contains a 11-bit address that directly points to a
location in the program memory space. There are two operands
associated with this addressing mode. Each operand contains a
byte of an address. This mode is used only for the long jump (JMP)
and JSR instructions.
This mode is used for the short jump (JP) instructions where the
operand is a value relative to the current PC address. With this
instruction, software is limited to the number of bytes it can jump,
-31 or +32.
Global Interrupt
Enable
G
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Interrupt