ace1202 Fairchild Semiconductor, ace1202 Datasheet - Page 19

• Manufacturer Part Number: ace1202
• Description: Arithmetic Controller Engine Acex ?for Low Power Applications
• Manufacturer: Fairchild Semiconductor

ACE1202 Product Family Rev. B.1
Timer 1 is a versatile 16-bit timer that can operate in one of four
modes:
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Timer 1 contains a 16-bit timer/counter register (TMR1), a 16-bit
auto-reload/capture register (T1RA), and an 8-bit control register
(T1CNTRL). All register are memory-mapped for simple access
through the core with both the 16-bit registers organized as a pair
of 8-bit register bytes {TMR1HI, TMR1LO} and {T1RAHI, T1RALO}.
Depending on the operating mode, the timer contains an external
input or output (T1) that is multiplexed with the I/O pin G2. By
12 and 13.
pulses of a specified width and duty cycle
of an external event
elapsed time between occurrences of external events
measures the difference between edges
0
0
0
0
1
1
1
1
1
1
0
1
1
0
0
1
0
0
1
1
x
x
x
x
x
x
0
1
0
1
mode, which counts occurrences
mode, which measures the
(PWM) mode, which generates
mode, which automatically
MODE 2
MODE 2
MODE 1 T1 Toggle
MODE 1 No T1 Toggle
MODE 3 Captures: T1 Pos. edge
MODE 3 Captures: T1 Neg. Edge
MODE 4 Difference Capture
MODE 4 Difference Capture
MODE 4 Difference Capture
MODE 4 Difference Capture
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T1PND
T1EN
M4S1
T1C3
T1C2
T1C1
T1C0
default, the TMR1 is reset to 0xFFFF, T1RA is reset to 0x0000,
and T1CNTRL is reset to 0x00.
The timer can be started or stopped through the T1CNTRL
register bit T1C0. When running, the timer counts down (decre-
ments) every clock cycle. Depending on the operating mode, the
timer’s clock is either the instruction clock or a transition on the T1
input. In addition, occurrences of timer underflow (transitions from
0x0000 to 0xFFFF/T1RA value) can either generate an interrupt
and/or toggle the T1 output pin.
Timer 1’s interrupt (TMRI1) can be enabled by interrupt enable
(T1EN) bit in the T1CNTRL register. When the timer interrupt is
enabled, depending on the operating mode, the source of the
interrupt is a timer underflow and/or a timer capture.
Reading and writing to the T1CNTRL register controls the timer’s
operation. By writing to the control bits, the user can enable or
disable the timer interrupts, set the mode of operation, and start or
stop the timer. The T1CNTRL register bits are described in Tables
Timer TIMER1 control bit 3 (see Table 13)
Timer TIMER1 control bit 2 (see Table 13)
Timer TIMER1 control bit 1 (see Table 13)
Timer TIMER1 run: 1 = Start timer, 0 = Stop timer;
or Timer TIMER1 underflow interrupt pending flag
in input capture mode
Timer1 interrupt pending flag: 1 = Timer1 interrupt
pending, 0 = Timer1 interrupt not pending
Timer1 interrupt enable bit: 1 = Timer1 interrupt enabled,
0 = Timer1 interrupt disabled
Capture type: 0 = Pulse capture, 1 = Cycle capture (see Table 13)
Reserved
TIMER1 Underflow
TIMER1 Underflow
Autoreload T1RA
Autoreload T1RA
Pos. T1 Edge
Neg. T1 Edge
Pos. to Neg.
Pos. to Pos.
Neg. to Pos.
Neg. to Neg.
T1 Pos. Edge
T1 Neg. Edge
Instruction Clock
Instruction Clock
Instruction Clock
Instruction Clock
Instruction Clock
Instruction Clock
Instruction Clock
Instruction Clock
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