dspic33fj128gp204 Microchip Technology Inc., dspic33fj128gp204 Datasheet - Page 95
dspic33fj128gp204
Manufacturer Part Number
dspic33fj128gp204
Description
High-performance, 16-bit Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet
1.DSPIC33FJ128GP204.pdf
(386 pages)
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REGISTER 7-5:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
R/W-0
T2IF
U-0
—
Unimplemented: Read as ‘0’
DMA1IF: DMA Channel 1 Data Transfer Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
U1RXIF: UART1 Receiver Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
SPI1IF: SPI1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
SPI1EIF: SPI1 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
T3IF: Timer3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
T2IF: Timer2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
IC2IF: Input Capture Channel 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
DMA0IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
T1IF: Timer1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
DMA1IF
OC2IF
R/W-0
R/W-0
IFS0: INTERRUPT FLAG STATUS REGISTER 0
‘1’ = Bit is set
W = Writable bit
R/W-0
AD1IF
R/W-0
IC2IF
DMA0IF
U1TXIF
R/W-0
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U1RXIF
R/W-0
R/W-0
T1IF
SPI1IF
OC1IF
R/W-0
R/W-0
x = Bit is unknown
SPI1EIF
R/W-0
R/W-0
IC1IF
DS70292C-page 93
INT0IF
R/W-0
R/W-0
T3IF
bit 8
bit 0
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