dspic33fj128gp204 Microchip Technology Inc., dspic33fj128gp204 Datasheet - Page 377

• Manufacturer Part Number: dspic33fj128gp204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

TABLE A-2:
© 2009 Microchip Technology Inc.
Section 10.0 “Power-Saving
Features”
Section 11.0 “I/O Ports”
Section 16.0 “Serial Peripheral
Interface (SPI)”
Section 18.0 “Universal
Asynchronous Receiver Transmitter
(UART)”
Section 19.0 “Enhanced CAN
(ECAN™) Module”
Section 21.0 “10-Bit/12-Bit Analog-
to-Digital Converter (ADC)”
Section 22.0 “Audio Digital-to-
Analog Converter (DAC)”
Section 23.0 “Comparator Module”
Section 24.0 “Real-Time Clock and
Calendar (RTCC)”
Section 27.0 “Special Features”
Section Name
MAJOR SECTION UPDATES (CONTINUED)
Added the following registers:
• PMD1: Peripheral Module Disable Control Register 1 (Register 10-1)
• PMD2: Peripheral Module Disable Control Register 2 (Register 10-2)
• PMD3: Peripheral Module Disable Control Register 3 (Register 10-3)
Removed Table 11-1 and added reference to pin diagrams for I/O pin
availability and functionality.
Added paragraph on ADPCFG register default values to Section 11.2
“Configuring Analog Port Pins”.
Added Note box regarding PPS functionality with input mapping to
Section 11.4.2.1 “Input Mapping”.
Added Note 2 and 3 to the SPIxCON1 register (see Register 16-2).
Updated the Notes in the UxMode register (see Register 18-1).
Updated the UTXINV bit settings in the UxSTA register and added Note 1
(see Register 18-2).
Changed bit 11 in the ECAN Control Register 1 (CiCTRL1) to Reserved (see
Register 19-1).
Replaced the ADC1 Module Block Diagrams with new diagrams (see
Figure 21-1 and Figure 21-2).
Updated bit values for ADCS<7:0> and added Notes 1 and 2 to the ADC1
Control Register 3 (AD1CON3) (see Register 21-3).
Added Note 2 to the ADC1 Input Scan Select Register Low (AD1CSSL) (see
Register 21-7).
Added Note 2 to the ADC1 Port Configuration Register Low (AD1PCFGL)
(see Register 21-8).
Updated the midpoint voltage in the last sentence of the first paragraph.
Updated the voltage swing values in the last sentence of the last paragraph
in Section 22.3 “DAC Output Format”.
Updated the Comparator Voltage Reference Block Diagram
(see Figure 23-2).
Updated the minimum positive adjust value for CAL<7:0> in the RTCC
Calibration and Configuration (RCFGCAL) Register (see Register 24-1).
Added Note 1 to the Device Configuration Register Map (see Table 27-1).
Updated Note 1 in the dsPIC33F Configuration Bits Description (see
Table 27-2).
Preliminary
Update Description
DS70292C-page 375