dspic33fj128gp204 Microchip Technology Inc., dspic33fj128gp204 Datasheet - Page 382

• Manufacturer Part Number: dspic33fj128gp204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

Reset
Reset Sequence.................................................................. 83
Resets ................................................................................. 75
S
Serial Peripheral Interface (SPI) ....................................... 197
Software Reset Instruction (SWR) ...................................... 81
Software Simulator (MPLAB SIM)..................................... 314
Software Stack Pointer, Frame Pointer
Special Features of the CPU............................................. 295
SPI Module
Symbols Used in Opcode Descriptions............................. 306
System Control
T
Temperature and Voltage Specifications
Timer1 ............................................................................... 183
Timer2/3 ............................................................................ 185
Timing Characteristics
Timing Diagrams
DS70292C-page 380
IPC7 (Interrupt Priority Control 7) ............................. 114
IPC8 (Interrupt Priority Control 8) ............................. 115
IPC9 (Interrupt Priority Control 9) ............................. 116
NVMCON (Flash Memory Control) ............................. 71
NVMKEY (Nonvolatile Memory Key) .......................... 72
OCxCON (Output Compare x Control) ..................... 195
OSCCON (Oscillator Control) ................................... 141
OSCTUN (FRC Oscillator Tuning) ............................ 145
PLLFBD (PLL Feedback Divisor) .............................. 144
PMD1 (Peripheral Module Disable Control Register 1)...
PMD2 (Peripheral Module Disable Control Register 2)...
PMD3 (Peripheral Module Disable Control Register 3)...
PxTCON (PWM Time Base Control)......... 263, 264, 265
RCON (Reset Control) ................................................ 76
RSCON (DCI Receive Slot Control).......................... 248
SPIxCON1 (SPIx Control 1) ...................................... 199
SPIxCON2 (SPIx Control 2) ...................................... 201
SPIxSTAT (SPIx Status and Control) ....................... 198
SR (CPU Status) ................................................... 26, 88
T1CON (Timer1 Control)........................................... 184
TCxCON (Input Capture x Control) ........................... 192
TSCON (DCI Transmit Slot Control) ......................... 248
TxCON (Type B Time Base Control) ........................ 188
TyCON (Type C Time Base Control) ........................ 189
UxMODE (UARTx Mode) .......................................... 212
UxSTA (UARTx Status and Control) ......................... 214
Illegal Opcode ....................................................... 75, 82
Trap Conflict.......................................................... 81, 82
Uninitialized W Register ........................................ 75, 82
CALLL Stack Frame.................................................... 60
SPI1 Register Map ...................................................... 47
Register Map............................................................... 59
AC ............................................................................. 326
CLKO and I/O ........................................................... 329
10-bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM
10-bit A/D Conversion (CHPS
12-bit A/D Conversion (ASAM = 0, SSRC = 000) ..... 353
Brown-out Situations ................................................... 81
DCI AC-Link Mode .................................................... 347
DCI Multi -Channel, I
ECAN I/O .................................................................. 349
151
152
153
= 0, SSRC = 000).............................................. 355
0, ASAM = 1, SSRC = 111, SAMC =
00001)
........................................................... 355
2
S Modes ................................. 345
= 01, SIMSAM =
Preliminary
Timing Requirements
Timing Specifications
U
UART Module
Universal Asynchronous Receiver Transmitter (UART) ... 211
Using the RCON Status Bits............................................... 82
V
Voltage Regulator (On-Chip) ............................................ 299
W
Watchdog Time-out Reset (WDTR).................................... 81
Watchdog Timer (WDT)............................................ 295, 300
WWW Address ................................................................. 381
WWW, On-Line Support ..................................................... 12
External Clock........................................................... 327
I2Cx Bus Data (Master Mode) .................................. 341
I2Cx Bus Data (Slave Mode) .................................... 343
I2Cx Bus Start/Stop Bits (Master Mode)................... 341
I2Cx Bus Start/Stop Bits (Slave Mode)..................... 343
Input Capture (CAPx) ............................................... 334
OC/PWM................................................................... 335
Output Compare (OCx)............................................. 334
Reset, Watchdog Timer, Oscillator Start-up Timer and
SPIx Master Mode (CKE = 0) ................................... 336
SPIx Master Mode (CKE = 1) ................................... 337
SPIx Slave Mode (CKE = 0) ..................................... 338
SPIx Slave Mode (CKE = 1) ..................................... 339
Timer1, 2 and 3 External Clock ................................ 332
CLKO and I/O ........................................................... 329
DCI AC-Link Mode.................................................... 348
DCI Multi-Channel, I
External Clock........................................................... 327
Input Capture ............................................................ 334
10-bit A/D Conversion Requirements ....................... 356
12-bit A/D Conversion Requirements ....................... 354
CAN I/O Requirements ............................................. 349
I2Cx Bus Data Requirements (Master Mode)........... 342
I2Cx Bus Data Requirements (Slave Mode)............. 344
Output Compare Requirements................................ 334
PLL Clock ................................................................. 328
QEI External Clock Requirements ............................ 333
QEI Index Pulse Requirements ................................ 336
Reset, Watchdog Timer, Oscillator Start-up Timer, Pow-
Simple OC/PWM Mode Requirements ..................... 335
SPIx Master Mode (CKE = 0) Requirements............ 336
SPIx Master Mode (CKE = 1) Requirements............ 337
SPIx Slave Mode (CKE = 0) Requirements.............. 338
SPIx Slave Mode (CKE = 1) Requirements.............. 340
Timer1 External Clock Requirements ....................... 332
Timer2 External Clock Requirements ....................... 333
Timer3 External Clock Requirements ....................... 333
UART1 Register Map............................................ 46, 47
Programming Considerations ................................... 300
Power-up Timer ................................................ 330
er-up Timer and Brown-out Reset Requirements...
331
2
S Modes.................................. 346
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