dspic33fj128gp204 Microchip Technology Inc., dspic33fj128gp204 Datasheet - Page 61

• Manufacturer Part Number: dspic33fj128gp204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

TABLE 4-33:
TABLE 4-34:
TABLE 4-35:
TABLE 4-36:
RCON
OSCCON
CLKDIV
PLLFBD
OSCTUN
ACLKCON
Legend:
Note
BSRAM
SSRAM
Legend:
Note
NVMCON
NVMKEY
Legend:
PMD1
PMD2
PMD3
Legend:
File Name
File Name
File Name
File Name
1:
2:
1:
Addr
074A
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values dependent on type of Reset.
OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
Addr
0752
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register is not present in devices with 4K RAM and 32K Flash memory.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0740
0742
0744
0746
0748
0750
Addr
0770
0772
0774
Addr
0760
0766
TRAPR IOPUWR
SYSTEM CONTROL REGISTER MAP
SECURITY REGISTER MAP
NVM REGISTER MAP
PMD REGISTER MAP
Bit 15
ROI
Bit 15
IC8MD
—
—
—
—
Bit 15
T5MD
Bit 15
—
—
WR
—
—
Bit 14
IC7MD
—
—
—
Bit 14
Bit 14
T4MD
Bit 14
WREN
—
—
—
—
SELACLK
COSC<2:0>
DOZE<2:0>
Bit 13
Bit 13
T3MD
—
—
—
Bit 13
WRERR
Bit 13
—
—
—
—
—
Bit 12
T2MD
Bit 12
Bit 12
AOSCMD<1:0>
—
—
—
Bit 12
—
—
—
—
—
—
(1)
Bit 11
T1MD
Bit 11
—
—
—
DOZEN
—
Bit 11
Bit 11
—
—
—
—
—
—
CMPMD
Bit 10
Bit 10
—
—
—
—
Bit 10
Bit 10
—
—
—
—
—
APSTSCLR<2:0>
RTCCMD
FRCDIV<2:0>
IC2MD
NOSC<2:0>
Bit 9
Bit 9
—
—
—
Bit 9
Bit 9
—
—
CM
—
—
PMPMD
DCIMD
IC1MD
Bit 8
Bit 8
—
—
VREGS
Bit 8
Bit 8
—
—
—
I2C1MD
CRCMD
Bit 7
CLKLOCK
ASRCSEL
Bit 7
—
—
—
EXTR
Bit 7
PLLPOST<1:0>
Bit 7
—
—
DAC1MD
U2MD
Bit 6
Bit 6
IOLOCK
—
—
ERASE
—
Bit 6
Bit 6
SWR
—
—
U1MD
Bit 5
SWDTEN
Bit 5
—
—
—
—
LOCK
Bit 5
Bit 5
—
—
—
PLLDIV<8:0>
SPI2MD
Bit 4
Bit 4
—
—
WDTO
Bit 4
—
—
Bit 4
NVMKEY<7:0>
—
—
—
SPI1MD
OC4MD
Bit 3
SLEEP
Bit 3
—
—
Bit 3
Bit 3
—
CF
—
TUN<5:0>
PLLPRE<4:0>
IW_ SSR
IW_BSR
OC3MD
Bit 2
Bit 2
IDLE
Bit 2
—
—
Bit 2
—
—
NVMOP<3:0>
LPOSCEN
IR_BSR
IR_SSR
OC2MD
Bit 1
C1MD
Bit 1
BOR
Bit 1
Bit 1
—
—
OSWEN
RL_BSR
RL_SSR
OC1MD
AD1MD
Bit 0
Bit 0
POR
Bit 0
Bit 0
—
—
Resets
Resets
Resets
Resets
xxxx
0300
3040
0030
0000
0000
0000
0000
0000
0000
0000
0000
0000
All
All
All
All
(1)
(2)