m58lt256jsb STMicroelectronics, m58lt256jsb Datasheet - Page 87

• Manufacturer Part Number: m58lt256jsb
• Description: 256 Mbit 16 Mb 16, Multiple Bank, Multilevel, Burst 1.8 V Supply, Secure Flash Memories
• Manufacturer: STMicroelectronics

M58LT256JST, M58LT256JSB
Table 44.
(P+32)h = 13Ch 01h
(P+33)h = 13Dh 00h
(P+34)h = 13Eh 11h
(P+35)h = 13Fh 00h
(P+3A)h = 144h 00h
(P+3B)h = 145h 02h
(P+3C)h = 146h 64h
(P+3D)h = 147h 00h
(P+3E)h = 148h 02h
(P+3F)h = 149h 03h
(P+36)h = 140h 00h
(P+37)h = 141h 02h
(P+38)h = 142h 0Eh
(P+39)h = 143h 00h
M58LT256JST
Offset
Bank and erase block region 2 information
Data
(P+3C)h = 146h
(P+3D)h = 147h
(P+42)h = 14Ch
(P+43)h = 14Dh
(P+3A)h = 144h
(P+3B)h = 145h
(P+3E)h = 148h
(P+3F)h = 149h
(P+40)h = 14Ah
(P+41)h = 14Bh
(P+44)h = 14Eh
(P+45)h = 14Fh
(P+46)h = 150h
(P+47)h = 151h
M58LT256JSB
Offset
Data
0Fh
0Fh Bank region 2 Erase Block type 1 information
00h
11h
00h
00h
01h
00h
00h
02h
64h Bank region 2 (Erase Block type 1)
00h
02h
03h
Number of identical banks within bank region 2
Number of program or erase operations allowed in
bank region 2:
Bits 0-3: number of simultaneous program
operations
Bits 4-7: number of simultaneous erase operations
Number of program or erase operations allowed in
other banks while a bank in this region is
programming
Bits 0-3: number of simultaneous program
operations
Bits 4-7: number of simultaneous erase operations
Number of program or erase operations allowed in
other banks while a bank in this region is erasing
Bits 0-3: number of simultaneous program
operations
Bits 4-7: number of simultaneous erase operations
Types of erase block regions in bank region 2
n = number of erase block regions with contiguous
same-size erase blocks.
Symmetrically blocked banks have one blocking
region.
Bits 0-15: n+1 = number of identical-sized erase
blocks
Bits 16-31: n × 256 = number of bytes in erase
block region
Minimum block erase cycles × 1000
Bank region 2 (Erase Block type 1): bits per cell,
internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5-7: reserved
Bank region 2 (Erase Block type 1): page mode
and synchronous mode capabilities (defined in
Table
Bit 0: page-mode reads permitted
Bit 1: synchronous reads permitted
Bit 2: synchronous writes permitted
Bits 3-7: reserved
41)
(2)
Description
Common Flash interface
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