m58lt256jsb STMicroelectronics, m58lt256jsb Datasheet - Page 44

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m58lt256jsb

Manufacturer Part Number
m58lt256jsb
Description
256 Mbit 16 Mb 16, Multiple Bank, Multilevel, Burst 1.8 V Supply, Secure Flash Memories
Manufacturer
STMicroelectronics
Datasheet

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Read modes
7
7.1
44/108
Read modes
Read operations can be performed in two different ways depending on the settings in the
Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read
operation is asynchronous. If the data output is synchronized with clock, the read operation
is synchronous.
The read mode and format of the data output are determined by the Configuration Register.
(See
and synchronous read operations.
Asynchronous read mode
In asynchronous read operations the clock signal is ‘don’t care’. The device outputs the data
corresponding to the address latched, that is the memory array, Status Register, common
Flash interface or the electronic signature, depending on the command issued. CR15 in the
Configuration Register must be set to ‘1’ for asynchronous operations.
Asynchronous read operations can be performed in two different ways, asynchronous
random access read and asynchronous page read. Only asynchronous page read takes full
advantage of the internal page storage so different timings are applied.
In asynchronous read mode a page of data is internally read and stored in a page buffer.
The page has a size of 8 words and is addressed by address inputs A0, A1 and A2. The first
read operation within the page has a longer access time (t
subsequent reads within the same page have much shorter access times (t
access time). If the page changes then the normal, longer timings apply again.
The device features an automatic standby mode. During asynchronous read operations,
after a bus inactivity of 150 ns, the device automatically switches to the automatic standby
mode. In this condition the power consumption is reduced to the standby value and the
outputs are still driven.
In asynchronous read mode, the WAIT signal is always de-asserted.
See
access read AC waveforms
Table 22: Asynchronous read AC
Section 6: Configuration Register
for details.
characteristics,
for details). All banks support both asynchronous
Figure 9: Asynchronous random
AVQV
M58LT256JST, M58LT256JSB
, random access time),
AVQV1
, page

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