m58lt256jsb STMicroelectronics, m58lt256jsb Datasheet - Page 39

• Manufacturer Part Number: m58lt256jsb
• Description: 256 Mbit 16 Mb 16, Multiple Bank, Multilevel, Burst 1.8 V Supply, Secure Flash Memories
• Manufacturer: STMicroelectronics

M58LT256JST, M58LT256JSB
6.3
6.4
6.5
6.6
Wait polarity bit (CR10)
The wait polarity bit sets the polarity of the Wait signal used in synchronous burst read
mode. During synchronous burst read mode the Wait signal indicates whether the data
output are valid or a WAIT state must be inserted.
When the Wait polarity bit is set to ‘0’, the Wait signal is active Low. When the wait polarity
bit is set to ‘1’ the Wait signal is active High.
Data output configuration bit (CR9)
The data output configuration bit configures the output to remain valid for either one or two
clock cycles during synchronous mode.
When the data output configuration bit is ’0’ the output data is valid for one clock cycle, and
when it is ’1’, the output data is valid for two clock cycles.
The data output configuration bit must be configured using the following condition:
where
If this condition is not satisfied, the data output configuration bit should be set to ‘1’ (two
clock cycles). Refer to
Wait configuration bit (CR8)
The wait configuration bit controls the timing of the Wait output pin, WAIT, in synchronous
burst read mode.
When WAIT is asserted, data is not valid, and when WAIT is de-asserted, data is valid.
When the wait configuration bit is Low (set to ’0’), the wait output pin is asserted during the
WAIT state. When the wait configuration bit is High (set to ’1’), the wait output pin is
asserted one data cycle before the WAIT state.
Burst type bit (CR7)
The burst type bit determines the sequence of addresses read during synchronous burst
reads.
The burst type bit is High (set to ’1’), as the memory outputs from sequential addresses only.
See
starting address in sequential mode.
Table 12: Burst type definition
t
t
t
t
K
K
QVK_CPU
KQV
> t
is the clock period
KQV
is the clock to data valid time.
+ t
is the data setup time required by the system CPU
QVK_CPU
Figure 5: X latency and data output configuration
for the sequence of addresses output from a given
Configuration Register
example.
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