w83877atd Winbond Electronics Corp America, w83877atd Datasheet - Page 73

• Manufacturer Part Number: w83877atd
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
4.3.7.5 Set5.Reg6, 7 - Receiver Frame Length FIFO (RFLFL/RFLFH) or Lost Frame Number
(LST_NU)
Receiver Frame Length FIFO (RFLFL/RFLFH):
These registers are 13-bit. Reading these registers will return received frame length. When read the
register of RFLFH will pop-up another frame status and frame length if FSFDR=1 (Set5.Reg4.Bit7).
Reset Value
Reset Value
LST_NU
RFLFL/
RFLFH
Reg.
FSFDR - Frame Status FIFO Data Ready
Indicates that there is valid data in frame status FIFO bottom.
LST_FR - Lost Frame
Set to 1 when one or more than one frame has been lost.
Reserved.
MX_LEX - Maximum Frame Length Exceed
Set to 1 when programmed maximum frame length defined Set4.Reg6 and Set4.Reg7 are
exceeded. This bit is frame status FIFO bottom. Reading this bit will return a valid value
when FSFDR=1 (Frame Status FIFO Data Ready).
PHY_ERR - Physical Error
During receiving data, any physical layer error, defined IrDA 1.1, will be set to 1 in this bit.
This bit is frame status FIFO bottom. Reading this bit will return a valid value when
FSFDR=1 (Frame Status FIFO Data Ready).
CRC_ERR - CRC Error
Set to 1 when a bad CRC is received in a frame. This CRC belongs to physical layer
defined in IrDA 1.1. This bit is frame status FIFO bottom. Reading this bit will return a valid
value when FSFDR=1 (Frame Status FIFO Data Ready).
RX_OV - Received Data Overrun
Set to 1 when Received data in FIFO overrun occurs.
FSF_OV - Frame Status FIFO Overrun
Set to 1 When frame status FIFO overrun occurs.
Bit 7
Bit 7
0
0
-
Bit 6
Bit 6
0
0
-
Bit 5
Bit 5
0
0
-
Bit 12
Bit 4
Bit 4
- 69 -
0
0
Bit 11
Bit 3
Bit 3
0
0
Publication Release Date: April 1998
Bit 10
Bit 2
Bit 2
0
0
W83877ATF
Bit 1
Bit 1
Bit 9
0
0
Version 0.51
Bit 0
Bit 0
Bit 8
0
0