w83877atd Winbond Electronics Corp America, w83877atd Datasheet - Page 71

• Manufacturer Part Number: w83877atd
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

4.3.7.2 Set5.Reg2 - Flow Control mode Operation (FC_MD)
These registers control flow control mode operation as shown in the table below.
Bit 7~5
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
4.3.7.3 Set5.Reg3 - Sets Select Register (SSR)
A write to this register will change Set of register. Reading this register will return EC
default Value
Reset Value
FC_MD
Reg.
Reg.
SSR
FC_MD2 FC_MD1 FC_MD0
FC_MD2 - Flow Control mode
When flow control state occurs, these bits will be loaded to AD_MD2~0 of advanced HSR
(Handshake Status Register). These three bits are defined the same as AD_MD2~0.
Reserved, write 0.
FC_DSW - Flow Control DMA Channel Swap
Write to 1, when flow control state occurs enables DMA channel of both transmitter and
receiver to be swapped.
EN_FD - Enable Flow DMA Control
Write to 1 enables use of DMA channel when flow control has occurred.
EN_BRFC - Enable Baud Rate Flow Control
Write to 1 enables FC_BLL/FC_BHL (Flow Control Baud Rate Divider Latch, in
Set5.Reg1~0) to be loaded to advanced baud rate divisor latch (ADBLL/ADBHL, in
Set2.Reg1~0).
EN_FC - Enable Flow Control
Write to 1 allows use of flow control function and activation of bit 7~1 of this register.
SSR7
Bit 7
Bit 7
0
1
FC_DSW
0
1
SSR6
Bit 6
Bit 6
0
1
SSR5
Bit 5
Bit 5
0
1
Next Mode After Flow Control Occurred
SSR4
Bit 4
Bit 4
- 67 -
0
0
-
Transmitter Channel
Receiver Channel
FC_DSW
SSR3
Bit 3
Bit 3
0
1
Publication Release Date: April 1998
EN_FD
SSR2
Bit 2
Bit 2
0
1
EN_BRFC EN_FC
W83877ATF
SRR1
Bit 1
Bit 1
16
0
0
.
Version 0.51
SRR0
Bit 0
Bit 0
0
0