w83877atd Winbond Electronics Corp America, w83877atd Datasheet - Page 140

• Manufacturer Part Number: w83877atd
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

EN24MX2:
DIS_BST(Bit3): Disable FDC DMA Burst Mode.
8.2.39 Configuration Register 31 (CR31), default=00H
When the device is in Extended Function mode and EFIR is 31H, the CR31 register can be accessed
through EFDR. The bit definitions are as follows:
SCIIRQ3 ~ SCIIRQ0 (Bit 7 - bit 4):
The four bits select one IRQ pin for the SCI signal except for dedicated SCI signal output pin. Any
unselected pin is in tri-state.
While in the Serial IRQ mode (IRQMODS=1, CR31 bit 2), the above selection is invalid and all the
IRQ signal pins, from IRQ_A to IRQ_H, are all in tri-state. The SCI interrupt output is dedicated to the
SERIRQ pin. For the host controller to correctly sample the SCI interrupt, the SCI interrupt should be
programmed to appear in one of IRQ/Data Frame sampling periods.
In Serial IRQ mode, the definition of SCIIQS3-SCIIQS0 (bit 7-bit 4) is as follows:
SCIIQS3-SCIIQS0 (bit 7-bit 4): Select the IRQ/Data sampling period on the SERIRQ pin.
CR31[7:4]
0
1
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
Using internal circuit type one to generate 48M Hz when CLKIN is 24M Hz. (Default)
Using internal circuit type two to generate 48M Hz when CLKIN is 24M Hz.
Enable FDC burst mode. (Default)
Disable FDC burst mode.
None (default)
IRQ_A
IRQ_B
IRQ_C
IRQ_D
IRQ_E
IRQ_F
IRQ_G
IRQ_H
7
6
5
4
Mapped IRQ pin
3
- 136 -
2
1
0
Publication Release Date: April 1998
reserved
reserved
IRQMODS
reserved
SCIIRQ0
SCIIRQ1
SCIIRQ2
SCIIRQ3
W83877ATF
Version 0.51