w83877atd Winbond Electronics Corp America, w83877atd Datasheet - Page 64

• Manufacturer Part Number: w83877atd
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

4.3.4 Set2 - Interrupt Status or UART FIFO Control Register (ISR/UFR)
These registers are only used in advanced modes.
4.3.4.1 Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL)
The two registers are the same as the legacy UART baud rate divisor latch in SET 1. Reg0~1. When
using advanced UART/SIR/ASK-IR mode operation, these registers should be programmed to set
baud rate. This is to prevent a backward operation occurring.
4.3.4.2 Reg2 - Advanced UART Control Register 1 (ADCR1)
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Advanced
Reset Value
Address
UART
Mode
Offset
0
1
2
3
4
5
6
7
BR_OUT
BR_OUT - Baud Rate Clock Output
Write to 1 enables the programmed baud rate clock to output to DTR pin. This bit is the
only test baud rate divisor.
Reserved, write 0.
EN_LOUT - Enable Loopback Output
Write to 1 enables output of transmitter data to IRTX pin during doing loopback
operation. Setting this bit can check output data with internal data.
D_CHSW - DMA TX/RX Channel Swap
If using signal DMA channel in MIR/FIR mode, then the DMA channel can be swapped.
Write to 1 enables output data during the ALOOP=1.
Register Name
Bit 7
Reserved
0
RXFDTH
TXFDTH
ADCR1
ADCR2
ABHL
ABLL
SSR
Bit 6
0
-
D_CHSW
Advanced Baud Rate Divisor Latch (Low Byte)
Advanced Baud Rate Divisor Latch (High Byte)
Advanced UART Control Register 1
Sets Select Register
Advanced UART Control Register 2
Transmitter FIFO Depth
Receiver FIFO Depth
0
1
EN_LOUT D_CHSW
Bit 5
0
Bit 4
- 60 -
0
DMA Channel Selected
Receiver (Default)
Register Description
Transmitter
ALOOP
Bit 3
0
-
Publication Release Date: April 1998
DMATHL
Bit 2
0
W83877ATF
DMA_F
Bit 1
0
Version 0.51
ADV_SL
Bit 0
0