w83877atd Winbond Electronics Corp America, w83877atd Datasheet - Page 44

• Manufacturer Part Number: w83877atd
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

BDLAB = 0
BDLAB = 0
BDLAB = 0
BDLAB = 1
BDLAB = 1
Register Address Base
A
A
B
C
D
E
F
8
8
9
8
9
3.2 Register Address
TABLE 3-1 UART Register Bit Map
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 mode.
Baudrate Divisor
Interrupt Control
Baudrate Divisor
Interrupt Status
Status Register
Buffer Register
UART Control
UART Status
User Defined
UART FIFO
(Read Only)
(Write Only)
(Read Only)
(Write Only)
Transmitter
Handshake
Handshake
Latch High
Latch Low
Receiver
Register
Register
Register
Register
Register
Register
Register
Register
Control
Control
Buffer
RBR
UFR
UCR
HCR
USR
HSR
UDR
TBR
BHL
ICR
ISR
BLL
"0" if Interrupt
RBR Data
RBR Data
RX Data
TX Data
(ERDRI)
Terminal
Interrupt
Toggling
Pending
(TCTS)
(DLS0)
Enable
Enable
Length
(RDR)
Ready
Select
Ready
(DTR)
Ready
FIFO
Bit 0
Bit 0
Data
Bit 0
Data
CTS
Bit 0
Bit 0
Bit 8
0
(ETBREI)
RX Data
TX Data
Interrupt
Interrupt
Request
Toggling
Overrun
(TDSR)
(DLS1)
Enable
RCVR
Length
(OER)
Empty
Status
Bit (0)
Select
(RTS)
Reset
FIFO
Send
Error
DSR
Bit 1
Bit 1
TBR
Data
Bit 1
Bit 1
Bit 1
Bit 9
to
1
Loopback
RI Falling
Stop Bits
Parity Bit
RX Data
(EUSRI)
TX Data
Interrupt
(MSBE)
(PBER)
Interrupt
Multiple
Enable
Enable
(FERI)
Status
Bit (1)
- 40 -
Reset
Bit 10
XMIT
FIFO
Input
Error
Edge
Bit 2
Bit 2
Bit 2
Bit 2
USR
RI
2
Bit Number
RX Data
TX Data
Interrupt
(EHSRI)
Interrupt
Toggling
No Stop
(NSER)
(TDCD)
Bit (2)**
Enable
Enable
Enable
Status
Select
(PBE)
Parity
Bit 11
DMA
Mode
HSR
Error
DCD
Bit 3
Bit 3
Bit 3
Bit 3
IRQ
Bit
Bit
3
Publication Release Date: April 1998
Reserved
Loopback
Detected
RX Data
TX Data
to Send
Internal
Enable
Enable
(SBD)
(EPE)
(CTS)
Parity
Silent
Bit 12
Clear
Even
Bit 4
Bit 4
Byte
Bit 4
Bit 4
4
0
0
W83877ATF
Reversed
RX Data
TX Data
Data Set
Bit Fixed
(TBRE)
Enable
PBFE)
Empty
Ready
(DSR)
Bit 13
Parity
Bit 5
Bit 5
TBR
Bit 5
Bit 5
5
0
0
0
Version 0.51
Active Level
RX Data
TX Data
Interrupt
Indicator
Enabled
(TSRE)
Silence
Enable
FIFOs
Empty
(SSE)
(LSB)
Bit 14
TSR
Ring
Bit 6
Bit 6
Bit 6
Bit 6
(RI)
RX
Set
**
6
0
0
Data Carrier
Active Level
Access Bit
Baud rate
RX FIFO
Indication
RX Data
(BDLAB)
(RFEI) **
TX Data
Interrupt
Enabled
(MSB)
Divisor
(DCD)
FIFOs
Detect
Latch
Bit 15
Error
Bit 7
Bit 7
Bit 7
Bit 7
RX
**
7
0
0