w83877atd Winbond Electronics Corp America, w83877atd Datasheet - Page 65

• Manufacturer Part Number: w83877atd
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

Bit 3:
Bit 2:
Bit 1:
Bit 0:
4.3.4.3 Reg3 - Sets Select Register (SSR)
Reading this register returns E0
4.3.4.4 Reg4 - Advanced UART Control Register 2 (ADCR2)
Bit 7:
Bit 6:
default Value
Advanced
Reset Value
UART
Mode
Reg.
SSR
DMATHL
0
1
DIS_BAC
ALOOP - All mode Loopback
Write to 1 enables loopback in all modes.
DMATHL - DMA Threshold Level
Sets DMA threshold level as shown in the table below.
DMA_F - DMA Fairness
ADV_SL - Advanced mode Select
Write to 1 selects advanced mode.
DIS_BACK - Disable Backward Operation
Write to 1, read or write BLL or BHL (Baud rate Divisor Latch Register, in
will disable backward legacy UART mode. When using legacy SIR/ASK-IR mode, this bit
should be set to 1 to avoid backward operation.
Reserved, write 0.
SSR7
Bit 7
Bit 7
K
1
0
DMA_F
SSR6
Bit 6
Bit 6
0
1
1
0
-
16
. Write it to select other register Set.
PR_DIV1 PR_DIV0 RX_FSZ1 RX_FSZ0 TX_FSZ1 TXFSZ0
16-Byte
SSR5
Bit 5
Bit 5
13
23
1
0
TX FIFO Threshold
DMA request (DREQ) is forced inactive after 10.5us
SSR4
Bit 4
Bit 4
- 61 -
0
0
No effect on DMA request.
Function Description
SSR3
Bit 3
Bit 3
32-Byte
0
0
13
7
Publication Release Date: April 1998
SSR2
Bit 2
Bit 2
0
0
RX FIFO Threshold
W83877ATF
SRR1
(16/32-Byte)
Bit 1
Bit 1
0
0
Set1.Reg0~1),
10
4
Version 0.51
SRR0
Bit 0
Bit 0
0
0