lpc47s457-ns Standard Microsystems Corp., lpc47s457-ns Datasheet - Page 82

• Manufacturer Part Number: lpc47s457-ns
• Description: Advanced I/o With X-bus Interface
• Manufacturer: Standard Microsystems Corp.

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7.
EPP 1.7 Read
The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. The chip inserts wait states
into the I/O read cycle when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The
read cycle can complete when nWAIT is inactive high.
Read Sequence of Operation:
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6.
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9.
Note 1: SPP and EPP can use 1 common register.
Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct
SMSC DS – LPC47S45x
The host initiates an I/O write cycle to the selected EPP register.
The chip places address or data on PData bus.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE
signal is valid.
If nWAIT is asserted, the chip inserts wait states into I/O write cycle until the peripheral deasserts nWAIT or a time-
out occurs.
The chip drives the final sync, deasserts nDATASTB or nADDRSTRB and latches the data from the internal data
bus for the PData bus.
Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
The host sets PDIR bit in the control register to a logic "1". This deasserts nWRITE and tri-states the PData bus.
The host initiates an I/O read cycle to the selected EPP register.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal
is valid.
If nWAIT is asserted, the chip inserts wait states into the I/O read cycle until the peripheral deasserts nWAIT or a
time-out occurs.
The Peripheral drives PData bus valid.
The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the
cycle.
The chip drives the final sync and deasserts nDATASTB or nADDRSTRB.
Peripheral tri-states the PData bus.
Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
nWRITE
PD<0:7>
INTR
WAIT
DATASTB
RESET
ADDRSTB
PE
SLCT
nERR
EPP read cycles, PCD is required to be a low.
SIGNAL
EPP
nWrite
Address/Data
Interrupt
nWait
nData Strobe
nReset
nAddress
Strobe
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Status
Error
EPP NAME
TYPE
I/O
O
O
O
O
Table 34 − EPP Pin Descriptions
I
I
I
I
I
DATASHEET
This signal is active low. It denotes a write operation.
Bi-directional EPP byte wide address and data bus.
This signal is active high and positive edge triggered. (Pass
through with no inversion, Same as SPP).
This signal is active low.
acknowledgement from the device that the transfer of data is
completed. It is driven active as an indication that the device is
ready for the next transfer.
This signal is active low. It is used to denote data read or write
operation.
This signal is active low. When driven active, the EPP device
is reset to its initial operational mode.
This signal is active low. It is used to denote address read or
write operation.
Same as SPP mode.
Same as SPP mode.
Same as SPP mode.
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EPP DESCRIPTION
It is driven inactive as a positive
Rev. 04-30-07