lpc47s457-ns Standard Microsystems Corp., lpc47s457-ns Datasheet - Page 187

• Manufacturer Part Number: lpc47s457-ns
• Description: Advanced I/o With X-bus Interface
• Manufacturer: Standard Microsystems Corp.

SMSC LPC47S45x
Vtr_CNT2
Default = 0x00 on
Vbat POR
Vtr_CNT3
Default = 0x00 on
Vbat POR
Vtr_CNT4
Default = 0x00 on
Vbat POR
SMBus2 Slave
Address and Enable
Default = 101011xxb
on VTR POR,
where xx is
determined by
SADR[1:0]
LPC_ARB
Arbitration Register
Default = 0x02
on VTR POR, VCC
POR, PCI Reset
Default = 000000x0b
on
Soft Reset (Note 9)
PM1_STS1
Default = 0x00 on
Vbat POR
PM1_STS2
(Note 8)
Default = 0x00 on
Vbat POR
Bit 7 cleared on VTR
POR.
NAME
Bit 1 is set/reset
arbitration logic,
Bit 0 is R/W by
and Read only
REG OFFSET
the LPC Bus,
(Read Only)
(Read Only)
(Read Only)
by the LPC
(Note 7)
(Note 7)
(Note 7)
by the
(R/W)
(R/W)
(R/W)
(hex)
Bus.
72
73
74
76
77
78
79
DATASHEET
Vtr_CNT2 (Byte 2)
Bit[7:0] = Bit[15:8] of the 32-bit VTR Power-On-Elapsed-Time
Vtr_CNT3 (Byte 3)
Bit[7:0] = Bit[23:16] of the 32-bit VTR Power-On-Elapsed-Time
Vtr_CNT4 (Byte 4)
This register contains the Most Significant Byte (MSB) of the 32 bit
VTR Power On Elapsed Time Counter.
Bit[7:0] = Bit[31:24] of the 32-bit VTR Power-On-Elapsed-Time
Bit [0] = Slave Address Bit 0 (Determined by state of the SADR0
on VTR power-up.)
Bit [1] = Slave Address Bit 1 (Determined by state of the SADR1
on VTR power-up.)
Bit [2] = Slave Address Bit 2
Bit [3] = Slave Address Bit 3
Bit [4] = Slave Address Bit 4
Bit [5] = Slave Address Bit 5
Bit [6] = Slave Address Bit 6
Bit [7] = SMBus2 Enable
0 = SMBus2 Controller Disabled
1 = SMBus2 Controller Enabled
When Bit 7 = 0, the SMBus2 controller will not respond to
addresses decoded on SDAT or drive SDAT or SCLK.
Bit [0] = LPC X-Bus Access Request (LPC_REQ)
Bit [1] = LPC X-Bus Access Grant (LPC_GNT)
Bit [2] = Reserved
Bit [3] = Reserved
Bit [4] = Reserved
Bit [5] = Reserved
Bit [6] = Reserved
Bit [7] = Reserved
Power Management 1 Status Register 1 (PM1_STS 1)
Bit[7:0] = Reserved. These bits always return a value of zero.
Power Management 1 Status Register 2 (PM1_STS 2)
Bit[0] PWRBTN_STS
This bit is set when the nPB_IN signal is asserted. While
PWRBTN_EN and PWRBTN_STS are both set an nIO_PME event
is raised. In the soft off state (nPS_ON float), a wake-up event
(nPS_ON transitions to active low) is generated regardless of the
setting of PWRBTN_EN.
This bit is only set by hardware and is reset by software writing a
one to this bit position, and by Vbat POR. Writing a 0 has no
effect.
Page 187 of 259
Counter
Counter
Counter
DESCRIPTION
Rev. 08-10-09