lpc47s457-ns Standard Microsystems Corp., lpc47s457-ns Datasheet - Page 130

• Manufacturer Part Number: lpc47s457-ns
• Description: Advanced I/o With X-bus Interface
• Manufacturer: Standard Microsystems Corp.

Control Register
Overview
The Control/Status register manages the SMBus operation and provides operational status (Table 63).
Control/Status register is located at the SMBus Base Address.
The Control register is write-only and is located at the SMBus Base Address. The Control register provides register
access control and control over SMBus signals.
The read-only component of the SMBus Base Address is the Status register, described in the Status Register
section, below.
Bit 7 PINC
Control register bit D7 is the Pending Interrupt Not Control bit. Writing the PINC bit to a logic ‘1’ deasserts all Status
register bits except for bit D0 nBB (Bus Busy). NOTE: the PINC bit has no affect on the nBB bit.
The PINC bit is self-clearing. Writing this bit to a logic ‘0’ has no effect.
Bit 6 ESO
Control register bit D6 is the Enable Serial Output control bit. ESO enables or disables the SMBus serial I/O.
When ESO is ‘1’, SMBus serial communication is enabled; communication with serial shift data register is enabled
and the bits in the Status register are available for reading.
Bit 5
RESERVED
Bit 4 TIE
The Timeout Interrupt Enable and the ENI bits determine whether or not an interrupt is generated as a result of an
SMBus timeout error.
When the TIE bit is ‘1’ and ENI is asserted, SMBus timeout errors will generate an interrupt.
When TIE is ‘0’, SMBus timeout errors will not generate interrupts, regardless of the state of ENI.
The TIE bit does not affect the Timeout Error bit TE in the Status register.
Bit 3 ENI
This bit enables the internal SMBus interrupt, nINT, which is generated when the PIN bit is asserted (‘0’).
Bit 2 and Bit 1 STA and STO
These bits control the generation of the SMBus Start condition and transmission of slave address and R/nW bit,
generation of repeated Start condition, and generation of the STOP condition (see Table 64). When transmitting the
command code or data byte the STA and STO bits should bit set for NOP function.
SMSC LPC47S45x
CONTROL
Type
Bit Def
Default
Status
Type
Bit Def
Default
Table 63 − SMBus Control/Status Register (SMBus/Base Address)
0x00 on VTR POR, VCC POR, PCI RESET or SOFT RESET
0x81 on VTR POR, VCC POR, PCI RESET or SOFT RESET
PINC
PIN
D7
D7
W
R
ES0
D6
D6
TE
W
R
DATASHEET
Reserved
STS
D5
D5
W
R
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BER
TIE
D4
D4
W
R
LRB
ENI
D3
D3
W
R
STA
AAS
D2
D2
W
R
STO
LAB
D1
D1
W
R
ACK
nBB
D0
D0
W
R
Rev. 08-10-09
The