lpc47s457-ns Standard Microsystems Corp., lpc47s457-ns Datasheet - Page 207
![no-image](/images/no-image-200.jpg)
lpc47s457-ns
Manufacturer Part Number
lpc47s457-ns
Description
Advanced I/o With X-bus Interface
Manufacturer
Standard Microsystems Corp.
Datasheet
1.LPC47S457-NS.pdf
(259 pages)
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Quantity
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Company:
Part Number:
LPC47S457-NS
Manufacturer:
Microchip Technology
Quantity:
10 000
- Current page: 207 of 259
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Note:
Note 1: The default value of the DMA Channel Select register for logical device 0 (FDD) is 0x02 and for logical
Note A. Logical Device IRQ and DMA Operation
1.
a)
b)
c)
d)
e)
SMSC LPC47S45x
IRQ and DMA Enable and Disable: Any time the IRQ or DMA channel for a logical block is disabled by a register bit
in that logical block, the IRQ and/or DMA channel must be disabled. This is in addition to the IRQ and DMA
channel disabled by the Configuration Registers (active bit or address not valid).
FDC: For the following cases, the IRQ and DMA channel used by the FDC are disabled.
Digital Output Register (Base+2) bit D3 (DMAEN) set to "0".
The FDC is in power down (disabled).
Serial Ports:
Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic "0", the serial port interrupt is disabled.
Parallel Port:
Keyboard Controller: Refer to the KBD section of this spec.
SMBus Controller:
Control Register Bit D3 (ENI) – When ENI is a logic “0” the SMBus interrupt is disabled.
DMA channels are disabled if not used/selected by any Logical Device. Refer to Note A.
device 3 is 0x04.
I.
ii.
SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to "0", IRQ is
disabled.
ECP Mode:
(1)
(2)
(FROM ECR REGISTER)
000
001
010
011
100
101
110
111
(DMA) dmaEn from ecr register. See table below.
IRQ - See table below.
MODE
PRINTER
CONFIG
TEST
FIFO
SPP
ECP
EPP
RES
DATASHEET
Page 207 of 259
CONTROLLED BY
IRQE
IRQE
IRQE
IRQE
IRQE
IRQ
(on)
(on)
(on)
CONTROLLED BY
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
DMA
Rev. 08-10-09
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