lpc47s457-ns Standard Microsystems Corp., lpc47s457-ns Datasheet - Page 214

• Manufacturer Part Number: lpc47s457-ns
• Description: Advanced I/o With X-bus Interface
• Manufacturer: Standard Microsystems Corp.

SMSC LPC47S45x
Base I/O Address 0 –
High Byte (Note 1)
Default = 0x00
on VTR POR, VCC
POR, PCI Reset and
Soft Reset
Base I/O Address 0 –
Low Byte (Note 1)
Default = 0x00
on VTR POR, VCC
POR, PCI Reset and
Soft Reset
Base I/O Address 1 –
High Byte (Note 1)
Default = 0x00
on VTR POR, VCC
POR, PCI Reset and
Soft Reset
NAME
NAME
Table 93 − X-Bus, Logical Device 8 [Logical Device Number = 0x08]
Table 91 − RTC, Logical Device 6 [Logical Device Number = 0x06]
0xF1 -
0xFF
R/W,
Read-Only
when the Base
I/O Address 1
– Low Byte
Register
bit[1]=1
REG INDEX
REG INDEX
0x60
0x61
0x62
R/W
R/W
Bit[3] KLATCH
(default)
Bit[2] Port 92 Select
Bit[1] Reserved
Bit[0] Reserved
Reserved - read as ‘0’
Register 0x60 sets the high byte of the base I/O address for
chip select 0.
Bits [7:0] =Address[15:8]
Note: Bits[15:12] must be ‘0’ since the chip performs 16-bit
address qualification on the base I/O addresses.
Register 0x61 sets the low byte of the base I/O address for chip
select 0.
Bits[7:0] = Address[7:0]
Register 0x62 sets the high byte of the base I/O address for
chip select 1.
Bits [7:0] =address[15:8]
Note: Bits[15:12] must be ‘0’ since the chip performs 16-bit
address qualification on the base I/O addresses.
= 1 MINT is the latched 8042 MINT
= 0 KINT is the 8042 KINT ANDed with Latched KINT
= 1 KINT is the latched 8042 KINT
DATASHEET
= 0 Port 92 Disabled
= 1 Port 92 Enabled
Page 214 of 259
DEFINITION
DEFINITION
Rev. 08-10-09
STATE
STATE