lpc47s457-ns Standard Microsystems Corp., lpc47s457-ns Datasheet - Page 222

• Manufacturer Part Number: lpc47s457-ns
• Description: Advanced I/o With X-bus Interface
• Manufacturer: Standard Microsystems Corp.

Note: XOSEL signal is used to differentiate between a 32kHz signal driven on the CLKI32 pin or an oscillator
connected between XTAL1 and XTAL2. If a 32kHz signal is connected to the CLKI32 pin, the XOSEL pin should be
pulled up to VTR. (A 10k Ω pull-up resistor is suggested) If a crystal oscillator is connected across XTAL1 and
XTAL2 or if no external clock is used then the XOSEL pin should be left unconnected. There is an internal pulldown
on this pin that will keep this pin low when not in use. The XTAL2/CLKI32 pin is an output when the XOSEL pin is left
unconnected and therefore, MUST NOT be grounded.
SMSC LPC47S45x
NAME
REG INDEX
Table 94 − Runtime Registers, Logical Device A
same time.
Note: if neither the VTR_POR_OFF bit nor the VTR_POR_EN bit is
set then the system will return to the state it was in prior to the loss of
VTR.
Bit[2] VTR_POR_EN
The enable bit for VTR POR. If VTR_POR_EN is set, the nPS_ON
pin will go active (low) and the machine will power-up as soon as a
VTR POR occurs. The software must not set VTR_POR_OFF and
VTR_POR_EN at the same time.
Note: if neither the VTR_POR_OFF bit nor the VTR_POR_EN bit is
set then the system will return to the state it was in prior to the loss of
VTR. This event is blocked when a power button override event
occurs (PWRBTNOR_STS bit set).
Bit[3] VTRPOR_STS
This bit is set upon a VTR POR. This bit is only set by hardware and
is reset by software writing a one to this bit position. Writing a 0 has
no effect. No PME is generated when nPS_ON goes active due to
VTR POR.
Bit[4] WAK_CTRL
0= do not set the WAK STS Bit (PM1_STS2 register)
1= set the WAK_STS bit as described in PM1_STS2 register.
Bit[5] SLP_CTRL
0=Writing a ‘1’ to the SLP_EN bit (PM1_CNTRL2 register) causes
the system to sequence into the sleeping state associated with the
SLP_TYPx field
1= Writing a ‘1’ to the SLP_EN bit does not sequence into the
sleeping state associated with the SLP_TYPx field, but generates an
SMI.
Bit[6] SMI_SCI_ENB
0= generate an SMI for enabled SCI events when the SCI_EN bit is
zero.
Note: To generate an IO_SMI# signal, Bit[7] EN_SMI in the SMI_EN2
register at offset 17h in the Runtime Register block must be set to ‘1’.
1= do not generate an SMI for enabled SCI events when the SCI_EN
bit is zero.
Note: when the SCI_EN bit is one, there will never be an SMI event
generated by the events in the PM1 or GPE1 registers. The GPE1
events can be enabled to generate an SMI separately through the
SMI_ENx registers.
Bit[7] PSOFF
Writing this bit to ‘1’ will force a software power down. Writing ‘0’ has
no effect. This bit is self-clearing.
DATASHEET
Page 222 of 259
DEFINITION
Rev. 08-10-09
STATE