lpc47s457-ns Standard Microsystems Corp., lpc47s457-ns Datasheet - Page 25

• Manufacturer Part Number: lpc47s457-ns
• Description: Advanced I/o With X-bus Interface
• Manufacturer: Standard Microsystems Corp.

6.3.1
The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz
electrical signal characteristics.
Note: The CLKRUN# signal is not implemented in this part.
LPC Cycles
The following cycle types are supported by the LPC protocol.
The LPC47S45x ignores cycles that it does not support.
Field Definitions
The data transfers are based on specific fields that are used in various combinations, depending on the cycle type.
These fields are driven onto the LAD[3:0] signal lines to communicate address, control and data information over the
LPC bus between the host and the LPC47S45x. See the Low Pin Count (LPC) Interface Specification Revision 1.0
from Intel, Section 4.2 for definition of these fields.
LFRAME# Usage
LFRAME# is used by the host to indicate the start of cycles and the termination of cycles due to an abort or time-out
condition. This signal is to be used by the LPC47S45x to know when to monitor the bus for a cycle.
This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start or stop of a
cycle, and that the LPC47S45x monitors the bus to determine whether the cycle is intended for it. The use of
LFRAME# allows the LPC47S45x to enter a lower power state internally. There is no need for the LPC47S45x to
monitor the bus when it is inactive, so it can decouple its state machines from the bus, and internally gate its clocks.
When the LPC47S45x samples LFRAME# active, it immediately stops driving the LAD[3:0] signal lines on the next
clock and monitor the bus for new cycle information.
The LFRAME# signal functions as described in the Low Pin Count (LPC) Interface Specification Revision 1.0.
I/O Read and Write Cycles
The LPC47S45x is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO accesses, and will
generally have minimal Sync times. The minimum number of wait-states between bytes is 1. EPP cycles will depend
on the speed of the external device, and may have much longer Sync times.
SMSC DS – LPC47S45x
LAD[3:0]
LFRAME#
PCI_RESET#
LDRQ#
IO_PME#
LPCPD#
SER_IRQ
PCI_CLK
SIGNAL
NAME
LPC INTERFACE SIGNAL DEFINITION
Output
TYPE
Input
Input
Input
Input
OD
I/O
I/O
CYCLE TYPE
DMA Write
DMA Read
I/O Write
I/O Read
Frame signal. Indicates start of new cycle and termination of broken cycle
PCI Reset. Used as LPC Interface Reset.
Encoded DMA/Bus Master request for the LPC interface.
Power Mgt Event signal. Allows the LPC47S45x to request wakeup.
Powerdown Signal. Indicates that the LPC47S45x should prepare for power to be shut
on the LPC interface.
Serial IRQ.
PCI Clock.
LPC address/data bus. Multiplexed command, address and data bus.
DATASHEET
Page 25 of 259
DESCRIPTION
TRANSFER SIZE
1 Byte
1 Byte
1 Byte
1 Byte
Rev. 04-30-07