lpc47s457-ns Standard Microsystems Corp., lpc47s457-ns Datasheet - Page 184
lpc47s457-ns
Manufacturer Part Number
lpc47s457-ns
Description
Advanced I/o With X-bus Interface
Manufacturer
Standard Microsystems Corp.
Datasheet
1.LPC47S457-NS.pdf
(259 pages)
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Part Number:
LPC47S457-NS
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SMSC LPC47S45x
Fan Tachometer
Register
Default = 0x00
Fan Preload Register
Default = 0x00
LED1
Default = 0x00
LED2
Default = 0x01
Keyboard Scan
Code
Default = 0x00
PM1_CNTRL1
Default = 0x00
on Vbat POR
on VTR POR
on VTR POR
on VTR POR
on VTR POR
on VTR POR
NAME
REG OFFSET
(R/W)
(R/W)
(R/W)
(R/W)
(hex)
R/W
(R)
5B
5D
5E
5F
59
60
DATASHEET
Fan Tachometer Register
Bit[7:0] The 8-bit FAN tachometer count. The number of counts of
the internal clock per pulse of the fan. The count value is
computed from Equation 1 in the Fan section. This value is the
final (maximum) count of the previous pulse (latched). The value in
this register may not be valid for up to 2 pulses following a write to
the preload register.
Fan Preload Register
Bit[7:0] The FAN tachometer preload. This is the initial value used
in the computation of the FAN count. Writing this register resets
the tachometer count.
Bit[1:0] LED1 Control
00=off
01=Blink at 1Hz rate with a 50% duty cycle (0.5 sec on, 0.5 sec off)
10=Blink at ½ HZ rate with a 25% duty cycle (0.5 sec on, 1.5 sec off)
11=on
Bits[7:2] Reserved
Bit[1:0] LED2 Control
00=off
01=Blink at 1Hz rate with a 50% duty cycle (0.5 sec on, 0.5 sec off)
10=Blink at ½ Hz rate with a 25% duty cycle (0.5 sec on, 1.5 sec off)
11=on
Bits[7:2] Reserved
Keyboard Scan Code
Bit[0] LSB of Scan Code
Bit[7] MSB of Scan Code
Power Management 1 Control Register 1 (PM1_CNTRL 1)
Bit[0] SCI_EN
When this bit is set, then the enabled PM1 and GPE1 power
management events will generate an nIO_PME interrupt. When
this bit is reset power management events will not generate an
nIO_PME interrupt. Instead, it will generate an SMI if the
SMI_SCI_EN bit is cleared. This bit does not affect the power
button or RTC wakeup event. This bit also does not affect GPE1
wakeup events.
Bits[7:1] Reserved. These bits always return a value 0.
. . .
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Page 184 of 259
DESCRIPTION
Rev. 08-10-09
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