isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 90

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09567
Product data
12.4.1 Bulk endpoints
12.4 End-Of-Transfer conditions
Table 73:
In DACK-only mode ISP1161’s DC uses the DACK2 signal as a data strobe. Input
signals RD and WR are ignored. This mode is used in CPU systems that have a
single address space for memory and I/O access. Such systems have no separate
MEMW and MEMR signals: the RD and WR signals are also used as memory data
strobes.
A DMA transfer to/from a bulk endpoint can be terminated by any of the following
conditions (bit names refer to the DcDMAConfiguration register, see
External EOT:
DMA operation and clear any remaining data in the current FIFO. For a double-
buffered endpoint the other (inactive) buffer is not affected.
When writing to an IN endpoint, an EOT will stop the DMA operation and the data
packet in the FIFO (even if it is smaller than the maximum packet size) will be sent to
the USB host at the next IN token.
DcDMACounter register:
setting bit CNTREN in the DcDMAConfiguration register. The ISP1161 has a 16-bit
DcDMACounter register, which specifies the number of bytes to be transferred. When
DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value from
Symbol
EOT
RD
WR
•
•
•
•
Fig 42. ISP1161’s device controller in DACK-only DMA mode.
An external End-Of-Transfer signal occurs on input EOT
The DMA transfer completes as programmed in the DcDMACounter register
(CNTREN = 1)
A short packet is received on an enabled OUT endpoint (SHORTP = 1)
DMA operation is disabled by clearing bit DMAEN.
DACK-only mode: pin functions
CONTROLLER
Description
End-Of-Transfer
read strobe
write strobe
ISP1161
DEVICE
When reading from an OUT endpoint, an external EOT will stop the
Rev. 02 — 13 December 2002
D0 to D15
DREQ2
DACK2
Full-speed USB single-chip host and device controller
An EOT from the DcDMACounter register is enabled by
RAM
I/O
I
I
I
…continued
DREQ
DACK
RD
WR
CONTROLLER
Function
DMA controller terminates the transfer
not used
not used
DMA
HLDA
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
HRQ
HRQ
HLDA
ISP1161
CPU
Table
004aaa010
87):
90 of 137