isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 22

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09567
Product data
Interrupt control:
The behavior of this bit is given in
Event A (see
with bit INTENA set to logic 0, an interrupt will not be generated at pin INT2.
However, it will be registered in the corresponding DcInterrupt register bit.
Event B (see
because bit SOF in the DcInterrupt register is already asserted.
Event C (see
be asserted. The bold dashed line shows the desired behavior of pin INT2.
Fig 21. DC interrupt logic.
Fig 22. Behavior of bit INTENA bit.
Pin INT2: HIGH = de-assert; LOW = assert (individual interrupts are enabled).
DcInterruptEnable register
DcInterrupt register
Figure
Figure
Figure
RESUME
IEP0OUT
SUSPND
EP0OUT
IERESM
IESUSP
RESET
IEP0IN
EP0IN
IERST
IESOF
IEEOT
IEP14
EP14
SOF
EOT
. ..
. ..
Rev. 02 — 13 December 2002
INT2 pin
Bit INTENA in the DcMode register is a global enable/disable bit.
occurs. For example,
an interrupt event
22): When an interrupt event occurs (for example, SOF interrupt)
(during this time,
22): When bit INTENA is set to logic 1, pin INT2 is asserted
22): If the firmware sets bit INTENA to logic 0, pin INT2 will still
SOF asserted.)
INTENA = 0
. .
.
. .
.
Full-speed USB single-chip host and device controller
MGT946
A
. .
.
. .
.
Figure
SOF asserted
INTENA = 1
DcMode register
22.
INTENA
B
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
LE
SOF asserted
INTENA = 0
C
LATCH
004aaa198
ISP1161
INT2
22 of 137