isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 50

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09567
Product data
Bit
Symbol
Reset
Access
reserved
7
0
10.1.5 HcInterruptEnable register (R/W: 04H/84H)
Table 15:
Each enable bit in the HcInterruptEnable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used
to control which events generate a hardware interrupt. When these three conditions
occur:
Writing logic 1 to a bit in this register sets the corresponding bit, whereas writing
logic 0 to a bit in this register leaves the corresponding bit unchanged. On a read, the
current value of this register is returned.
Code (Hex): 04 — read
Code (Hex): 84 — write
Bit
31 to 7
6
5
4
3
2
1
0
•
•
•
•
RHSC
A bit is set in the HcInterruptStatus register
The corresponding bit in the HcInterruptEnable register is set
The MasterInterruptEnable bit is set
Then a hardware interrupt is requested on the host bus.
6
0
HcInterruptStatus register: bit description
Symbol
-
RHSC
FNO
UE
RD
SF
-
SO
FNO
5
0
Rev. 02 — 13 December 2002
Description
reserved
RootHubStatusChange: This bit is set when the content of
HcRhStatus or the content of any of
HcRhPortStatus[NumberofDownstreamPort] has changed.
FrameNumberOverflow: This bit is set when the MSB of
HcFmNumber (bit 15) changes value, from logic 0 to 1 or from
logic 1 to 0.
UnrecoverableError: This bit is set when the HC detects a
system error not related to USB. The HC should not proceed with
any processing nor signaling before the system error has been
corrected. The HCD clears this bit after HC has been reset.
PHCI: Always set to logic 0.
ResumeDetected: This bit is set when the HC detects that a
device on the USB is asserting resume signaling. It is the transition
from no resume signaling to resume signaling causing this bit to be
set. This bit is not set when HCD sets the USBRESUME state.
StartOfFrame: At the start of each frame, this bit is set by the HC
and an SOF generated.
reserved
SchedulingOverrun: This bit is set when USB schedules for
current frame overruns. A scheduling overrun will also cause the
SchedulingOverrunCount of HcCommandStatus to be
incremented.
Full-speed USB single-chip host and device controller
UE
4
0
R/W
RD
3
0
SF
2
0
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
reserved
1
0
ISP1161
50 of 137
SO
0
0